-/ {
+/*
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/clock/rockchip,rk3288.h>
+
+/{
+ clocks {
+ compatible = "rockchip,rk-clocks";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xFF760000 0x01b0>;
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "xin24m";
+ clock-frequency = <24000000>;
+ };
+
+ xin12m: xin12m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&xin24m>;
+ clock-output-names = "xin12m";
+ clock-frequency = <12000000>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "xin32k";
+ clock-frequency = <32000>;
+ };
+
+ io_27m_in: io_27m_in {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "io_27m_in";
+ clock-frequency = <27000000>;
+ };
+
+ dummy: dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ i2s_clkin: i2s_clkin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "i2s_clkin";
+ clock-frequency = <0>;
+ };
+
+ edp_24m_clkin: edp_24m_clkin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "edp_24m_clkin";
+ clock-frequency = <0>;
+ };
+
+ gmac_clkin: gmac_clkin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "gmac_clkin";
+ clock-frequency = <0>;
+ };
+
+ clk_hsadc_ext: clk_hsadc_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "clk_hsadc_ext";
+ clock-frequency = <0>;
+ };
+
+ jtag_clkin: jtag_clkin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "jtag_clkin";
+ clock-frequency = <0>;
+ };
+
+ pclkin_cif: pclkin_cif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "pclkin_cif";
+ clock-frequency = <0>;
+ };
+
+ pclkin_isp: pclkin_isp {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "pclkin_isp";
+ clock-frequency = <0>;
+ };
+
+ clk_otgphy0_480m: clk_otgphy0_480m {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_gates13 4>;
+ clock-output-names = "clk_otgphy0_480m";
+ clock-div = <1>;
+ clock-mult = <20>;
+ #clock-cells = <0>;
+ };
+
+ clk_otgphy1_480m: clk_otgphy1_480m {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_gates13 5>;
+ clock-output-names = "clk_otgphy1_480m";
+ clock-div = <1>;
+ clock-mult = <20>;
+ #clock-cells = <0>;
+ };
+
+ clk_otgphy2_480m: clk_otgphy2_480m {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_gates13 6>;
+ clock-output-names = "clk_otgphy2_480m";
+ clock-div = <1>;
+ clock-mult = <20>;
+ #clock-cells = <0>;
+ };
+
+ clk_hsadc_inv: clk_hsadc_inv {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_hsadc_out>;
+ clock-output-names = "clk_hsadc_inv";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ pclkin_cif_inv: pclkin_cif_inv {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_gates16 0>;
+ clock-output-names = "pclkin_cif_inv";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ pclkin_isp_inv: pclkin_isp_inv {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_gates16 3>;
+ clock-output-names = "pclkin_isp_inv";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_vepu: hclk_vepu {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_vepu>;
+ clock-output-names = "hclk_vepu";
+ clock-div = <4>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_vdpu: hclk_vdpu {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_vdpu>;
+ clock-output-names = "hclk_vdpu";
+ clock-div = <4>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ clock_regs {
+ compatible = "rockchip,rk-clock-regs";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* PLL control regs */
+ pll_cons {
+ compatible = "rockchip,rk-pll-cons";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges ;
+
+ clk_apll: pll-clk@0000 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0000 0x10>;
+ mode-reg = <0x0050 0>;
+ status-reg = <0x0284 6>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_apll";
+ rockchip,pll-type = <CLK_PLL_3288_APLL>;
+ #clock-cells = <0>;
+ };
+
+ clk_dpll: pll-clk@0010 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0010 0x10>;
+ mode-reg = <0x0050 4>;
+ status-reg = <0x0284 5>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_dpll";
+ rockchip,pll-type = <CLK_PLL_3188PLUS>;
+ #clock-cells = <0>;
+ };
+
+ clk_cpll: pll-clk@0020 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0020 0x10>;
+ mode-reg = <0x0050 8>;
+ status-reg = <0x0284 7>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_cpll";
+ rockchip,pll-type = <CLK_PLL_3188PLUS>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_gpll: pll-clk@0030 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0030 0x10>;
+ mode-reg = <0x0050 12>;
+ status-reg = <0x0284 8>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_gpll";
+ rockchip,pll-type = <CLK_PLL_3188PLUS>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_npll: pll-clk@0040 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0040 0x10>;
+ mode-reg = <0x0050 14>;
+ status-reg = <0x0284 9>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_npll";
+ rockchip,pll-type = <CLK_PLL_3188PLUS>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ /* Select control regs */
+ clk_sel_cons {
+ compatible = "rockchip,rk-sel-cons";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clk_sel_con0: sel-con@0060 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0060 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_core_m0: aclk_core_m0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 4>;
+ clocks = <&clk_core>;
+ clock-output-names = "aclk_core_m0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ aclk_core_mp: aclk_core_mp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <4 4>;
+ clocks = <&clk_core>;
+ clock-output-names = "aclk_core_mp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ clk_core_div: clk_core_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_core";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
+ rockchip,flags = <(CLK_GET_RATE_NOCACHE |
+ CLK_SET_RATE_NO_REPARENT)>;
+ };
+
+ /* reg[14:13]: reserved */
+
+ clk_core: clk_core_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_apll>, <&clk_gates0 2>;
+ clock-output-names = "clk_core";
+ #clock-cells = <0>;
+ };
+
+ };
+
+
+ clk_sel_con1: sel-con@0064 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0064 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_bus: aclk_bus_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 3>;
+ clocks = <&aclk_bus_src_div>;
+ clock-output-names = "aclk_bus";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ aclk_bus_src_div: aclk_bus_src_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <3 5>;
+ clocks = <&aclk_bus_src>;
+ clock-output-names = "aclk_bus_src";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ hclk_bus: hclk_bus_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 2>;
+ clocks = <&aclk_bus>;
+ clock-output-names = "hclk_bus";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x3 4>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[11:10]: reserved */
+
+ pclk_bus: pclk_bus_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <12 3>;
+ clocks = <&aclk_bus>;
+ clock-output-names = "pclk_bus";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ aclk_bus_src: aclk_bus_src_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_gates0 11>, <&clk_gates0 10>;
+ clock-output-names = "aclk_bus_src";
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con2: sel-con@0068 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0068 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_tsadc: clk_tsadc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 6>;
+ clocks = <&xin32k>;
+ clock-output-names = "clk_tsadc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7:6]: reserved */
+
+ testout_div: testout_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&dummy>;
+ clock-output-names = "testout_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[15:13]: reserved */
+ };
+
+ clk_sel_con3: sel-con@006c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x006c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart4_div: clk_uart4_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart_pll_mux>;
+ clock-output-names = "clk_uart4_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_uart4: uart4_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>;
+ clock-output-names = "clk_uart4";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_UART>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[15:10]: reserved */
+
+ };
+
+ clk_sel_con4: sel-con@0070 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0070 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s0_pll_div: i2s0_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_i2s_pll>;
+ clock-output-names = "clk_i2s_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_i2s0: i2s0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_i2s_pll>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>;
+ clock-output-names = "clk_i2s0";
+ #clock-cells = <0>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[11:10]: reserved */
+
+ clk_i2s0_out: i2s0_outclk_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 1>;
+ clocks = <&clk_i2s0>, <&xin12m>;
+ clock-output-names = "clk_i2s0_out";
+ #clock-cells = <0>;
+ };
+
+ /* reg[14:13]: reserved */
+
+ clk_i2s_pll: i2s_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_i2s_pll";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+ };
+
+ clk_sel_con5: sel-con@0074 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0074 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spdif_pll_div: spdif_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_spdif_pll>;
+ clock-output-names = "spdif_pll_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_spdif: spdif_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&spdif_pll_div>, <&spdif_frac>, <&xin12m>;
+ clock-output-names = "clk_spdif";
+ #clock-cells = <0>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[14:10]: reserved */
+
+ clk_spdif_pll: spdif_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_spdif_pll";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con6: sel-con@0078 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0078 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_isp_div: clk_isp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 6>;
+ clocks = <&clk_isp>;
+ clock-output-names = "clk_isp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_isp: clk_isp_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "clk_isp";
+ #clock-cells = <0>;
+ };
+
+ clk_isp_jpe_div: clk_isp_jpe_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 6>;
+ clocks = <&clk_isp_jpe>;
+ clock-output-names = "clk_isp_jpe";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_isp_jpe: clk_isp_jpe_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "clk_isp_jpe";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con7: sel-con@007c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x007c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart4_frac: uart4_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart4_div>;
+ clock-output-names = "uart4_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con8: sel-con@0080 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0080 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s0_frac: i2s0_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_i2s_pll>;
+ clock-output-names = "i2s0_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con9: sel-con@0084 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0084 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spdif_frac: spdif_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&spdif_pll_div>;
+ clock-output-names = "spdif_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con10: sel-con@0088 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0088 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_peri: aclk_peri_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_peri_mux>;
+ clock-output-names = "aclk_peri";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7:5]: reserved */
+
+ hclk_peri: hclk_peri_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 2>;
+ clocks = <&aclk_peri>;
+ clock-output-names = "hclk_peri";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x2 4>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[11:10]: reserved */
+
+ pclk_peri: pclk_peri_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <12 2>;
+ clocks = <&aclk_peri>;
+ clock-output-names = "pclk_peri";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x2 4
+ 0x3 8>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[14]: reserved */
+
+ aclk_peri_mux: aclk_peri_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "aclk_peri_mux";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con11: sel-con@008c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x008c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_sdmmc0_div: clk_sdmmc0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 6>;
+ clocks = <&clk_sdmmc0>;
+ clock-output-names = "clk_sdmmc0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ clk_sdmmc0: clk_sdmmc0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clock-output-names = "clk_sdmmc0";
+ #clock-cells = <0>;
+ };
+
+ clk_hsicphy_12m_div: clk_hsicphy_12m_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 6>;
+ clocks = <&clk_hsicphy_480m>;
+ clock-output-names = "clk_hsicphy_12m_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con12: sel-con@0090 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0090 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_sdio0_div: clk_sdio0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 6>;
+ clocks = <&clk_sdio0>;
+ clock-output-names = "clk_sdio0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ clk_sdio0: clk_sdio0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clock-output-names = "clk_sdio0";
+ #clock-cells = <0>;
+ };
+
+ clk_emmc_div: clk_emmc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 6>;
+ clocks = <&clk_emmc>;
+ clock-output-names = "clk_emmc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ clk_emmc: clk_emmc_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clock-output-names = "clk_emmc";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con13: sel-con@0094 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0094 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart0_pll_div: clk_uart0_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart0_pll>;
+ clock-output-names = "clk_uart0_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_uart0: uart0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
+ clock-output-names = "clk_uart0";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_UART>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[10]: reserved */
+
+ usbphy_480m: usbphy_480m_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <11 2>;
+ clocks = <&clk_otgphy0_480m>, <&clk_otgphy1_480m>, <&clk_otgphy2_480m>;
+ clock-output-names = "usbphy_480m";
+ #clock-cells = <0>;
+ };
+
+ clk_uart0_pll: clk_uart0_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <13 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
+ clock-output-names = "clk_uart0_pll";
+ #clock-cells = <0>;
+ };
+
+ clk_uart_pll_mux: clk_uart_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_uart_pll_mux";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con14: sel-con@0098 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0098 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart1_div: clk_uart1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart_pll_mux>;
+ clock-output-names = "clk_uart1_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_uart1: uart1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
+ clock-output-names = "clk_uart1";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_UART>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[15:10]: reserved */
+ };
+
+ clk_sel_con15: sel-con@009c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x009c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart2_div: clk_uart2_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart_pll_mux>;
+ clock-output-names = "clk_uart2_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_uart2: uart2_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
+ clock-output-names = "clk_uart2";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_UART>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[15:10]: reserved */
+ };
+
+ clk_sel_con16: sel-con@00a0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00a0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart3_div: clk_uart3_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart_pll_mux>;
+ clock-output-names = "clk_uart3_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_uart3: uart3_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>;
+ clock-output-names = "clk_uart3";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_UART>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[15:10]: reserved */
+ };
+
+ clk_sel_con17: sel-con@00a4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00a4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0_frac: uart0_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart0_pll>;
+ clock-output-names = "uart0_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con18: sel-con@00a8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00a8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart1_frac: uart1_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart1_div>;
+ clock-output-names = "uart1_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con19: sel-con@00ac {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00ac 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart2_frac: uart2_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart2_div>;
+ clock-output-names = "uart2_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con20: sel-con@00b0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00b0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart3_frac: uart3_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart3_div>;
+ clock-output-names = "uart3_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con21: sel-con@00b4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00b4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_mac_pll: clk_mac_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <0 2>;
+ clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_mac_pll";
+ #clock-cells = <0>;
+ };
+
+ /* reg[3:2]: reserved */
+
+ clk_mac: clk_mac_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <4 1>;
+ clocks = <&clk_mac_pll>, <&gmac_clkin>;
+ clock-output-names = "clk_mac";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MAC_REF>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[7:5]: reserved */
+
+ clk_mac_pll_div: clk_mac_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_mac_pll>;
+ clock-output-names = "clk_mac_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[15:13]: reserved */
+ };
+
+ clk_sel_con22: sel-con@00b8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00b8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_hsadc_pll: clk_hsadc_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <0 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_hsadc_pll";
+ #clock-cells = <0>;
+ };
+/*
+ wifi_pll_mux: wifi_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <1 1>;
+ clocks = <&>, <&>;
+ clock-output-names = "wifi_pll_mux";
+ #clock-cells = <0>;
+ };
+*/
+
+ /* reg[3:2]: reserved */
+
+ clk_hsadc_out: clk_hsadc_out {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <4 1>;
+ clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
+ clock-output-names = "clk_hsadc_out";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_HSADC>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[6:5]: reserved */
+
+ clk_hsadc: clk_hsadc {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <7 1>;
+ clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
+ clock-output-names = "clk_hsadc";
+ #clock-cells = <0>;
+ };
+
+ clk_hsadc_pll_div: clk_hsadc_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 8>;
+ clocks = <&clk_hsadc_pll>;
+ clock-output-names = "clk_hsadc_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+ };
+/*
+ clk_sel_con23: sel-con@00bc {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00bc 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ wifi_frac: wifi_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&>;
+ clock-output-names = "wifi_frac";
+ / numerator denominator /
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <>;
+ #clock-cells = <0>;
+ };
+ };
+*/
+
+ clk_sel_con24: sel-con@00c0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00c0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* reg[7:0]: reserved */
+
+ clk_saradc: clk_saradc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 8>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_saradc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con25: sel-con@00c4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00c4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_spi0_div: clk_spi0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_spi0>;
+ clock-output-names = "clk_spi0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_spi0: clk_spi0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <7 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_spi0";
+ #clock-cells = <0>;
+ };
+
+ clk_spi1_div: clk_spi1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 7>;
+ clocks = <&clk_spi1>;
+ clock-output-names = "clk_spi1";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_spi1: clk_spi1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_spi1";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con26: sel-con@00c8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00c8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ddr_div: ddr_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 2>;
+ clocks = <&clk_ddr>;
+ clock-output-names = "clk_ddr";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x3 4>;
+ #clock-cells = <0>;
+ rockchip,flags = <(CLK_GET_RATE_NOCACHE |
+ CLK_SET_RATE_NO_REPARENT)>;
+ rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
+ };
+
+ clk_ddr: ddr_clk_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <2 1>;
+ clocks = <&clk_dpll>, <&clk_gpll>;
+ clock-output-names = "clk_ddr";
+ #clock-cells = <0>;
+ };
+
+ /* reg[5:3]: reserved */
+
+ clk_crypto: crypto_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <6 2>;
+ clocks = <&aclk_bus>;
+ clock-output-names = "clk_crypto";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ clk_cif_pll: clk_cif_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_cif_pll";
+ #clock-cells = <0>;
+ };
+
+ clk_cif_out_div: clk_cif_out_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <9 5>;
+ clocks = <&clk_cif_out>;
+ clock-output-names = "clk_cif_out";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[14]: reserved */
+
+ clk_cif_out: clk_cif_out_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cif_pll>, <&xin24m>;
+ clock-output-names = "clk_cif_out";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con27: sel-con@00cc {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00cc 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dclk_lcdc0: dclk_lcdc0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <0 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "dclk_lcdc0";
+ #clock-cells = <0>;
+ };
+
+ /* reg[7:2]: reserved */
+
+ dclk_lcdc0_div: dclk_lcdc0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 8>;
+ clocks = <&dclk_lcdc0>;
+ clock-output-names = "dclk_lcdc0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+ };
+
+ clk_sel_con28: sel-con@00d0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00d0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_edp_div: clk_edp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 6>;
+ clocks = <&clk_edp>;
+ clock-output-names = "clk_edp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_edp: clk_edp_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "clk_edp";
+ #clock-cells = <0>;
+ };
+
+ hclk_vio: hclk_vio_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&aclk_vio0>;
+ clock-output-names = "hclk_vio";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[14:13]: reserved */
+
+ clk_edp_24m: edp_24m_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&edp_24m_clkin>, <&xin24m>;
+ clock-output-names = "clk_edp_24m";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con29: sel-con@00d4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00d4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_hsicphy_480m: clk_hsicphy_480m_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <0 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "clk_hsicphy_480m";
+ #clock-cells = <0>;
+ };
+
+ clk_hsicphy_12m: hsicphy_12m_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <2 1>;
+ clocks = <&clk_gates13 9>, <&clk_hsicphy_12m_div>;
+ clock-output-names = "clk_hsicphy_12m";
+ #clock-cells = <0>;
+ };
+
+ clkin_isp: clkin_isp {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <3 1>;
+ clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
+ clock-output-names = "clkin_isp";
+ #clock-cells = <0>;
+ };
+
+ clkin_cif: clkin_cif {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <4 1>;
+ clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
+ clock-output-names = "clkin_cif";
+ #clock-cells = <0>;
+ };
+
+ /* reg[5]: reserved */
+
+ dclk_lcdc1: dclk_lcdc1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "dclk_lcdc1";
+ #clock-cells = <0>;
+ };
+
+ dclk_lcdc1_div: dclk_lcdc1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 8>;
+ clocks = <&dclk_lcdc1>;
+ clock-output-names = "dclk_lcdc1";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+ };
+
+ clk_sel_con30: sel-con@00d8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00d8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_rga_div: aclk_rga_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_rga>;
+ clock-output-names = "aclk_rga";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[5]: reserved */
+
+ aclk_rga: aclk_rga_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "aclk_rga";
+ #clock-cells = <0>;
+ };
+
+ clk_rga_div: clk_rga_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_rga>;
+ clock-output-names = "clk_rga";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[13]: reserved */
+
+ clk_rga: clk_rga_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "clk_rga";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con31: sel-con@00dc {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00dc 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_vio0_div: aclk_vio0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_vio0>;
+ clock-output-names = "aclk_vio0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[5]: reserved */
+
+ aclk_vio0: aclk_vio0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "aclk_vio0";
+ #clock-cells = <0>;
+ };
+
+ aclk_vio1_div: aclk_vio1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&aclk_vio1>;
+ clock-output-names = "aclk_vio1";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[13]: reserved */
+
+ aclk_vio1: aclk_vio1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "aclk_vio1";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con32: sel-con@00e0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00e0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_vepu_div: clk_vepu_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_vepu>;
+ clock-output-names = "clk_vepu";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[5]: reserved */
+
+ clk_vepu: clk_vepu_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "clk_vepu";
+ #clock-cells = <0>;
+ };
+
+ clk_vdpu_div: clk_vdpu_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_vdpu>;
+ clock-output-names = "clk_vdpu";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[13]: reserved */
+
+ clk_vdpu: clk_vdpu_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "clk_vdpu";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con33: sel-con@00e4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00e4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pclk_pd_pmu: pclk_pd_pmu_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_gpll>;
+ clock-output-names = "pclk_pd_pmu";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7:5]: reserved */
+
+ pclk_pd_alive: pclk_pd_alive {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_gpll>;
+ clock-output-names = "pclk_pd_alive";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[15:13]: reserved */
+ };
+
+ clk_sel_con34: sel-con@00e8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00e8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_gpu_div: clk_gpu_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_gpu>;
+ clock-output-names = "clk_gpu";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[5]: reserved */
+
+ clk_gpu: clk_gpu_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
+ clock-output-names = "clk_gpu";
+ #clock-cells = <0>;
+ };
+
+ clk_sdio1_div: clk_sdio1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 6>;
+ clocks = <&clk_sdio1>;
+ clock-output-names = "clk_sdio1";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ clk_sdio1: clk_sdio1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clock-output-names = "clk_sdio1";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con35: sel-con@00ec {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00ec 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_tsp_div: clk_tsp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_tsp>;
+ clock-output-names = "clk_tsp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[5]: reserved */
+
+ clk_tsp: clk_tsp_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "clk_tsp";
+ #clock-cells = <0>;
+ };
+
+ clk_tspout_div: clk_tspout_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_tspout>;
+ clock-output-names = "clk_tspout";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[13]: reserved */
+
+ clk_tspout: clk_tspout_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
+ clock-output-names = "clk_tspout";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con36: sel-con@00f0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00f0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_core0: clk_core0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 3>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_core0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* reg[3]: reserved */
+
+ clk_core1: clk_core1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <4 3>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_core1";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_core2: clk_core2_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 3>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_core2";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* reg[11]: reserved */
+
+ clk_core3: clk_core3_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <12 3>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_core3";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* reg[15]: reserved */
+ };
+
+ clk_sel_con37: sel-con@00f4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00f4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_l2ram: clk_l2ram_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 3>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_l2ram";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* reg[3]: reserved */
+
+ atclk_core: atclk_core_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <4 5>;
+ clocks = <&clk_core>;
+ clock-output-names = "atclk_core";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ pclk_dbg_src: pclk_core_dbg_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <9 5>;
+ clocks = <&clk_core>;
+ clock-output-names = "pclk_dbg_src";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* reg[15:14]: reserved */
+ };
+
+ clk_sel_con38: sel-con@00f8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00f8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_nandc0_div: clk_nandc0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_nandc0>;
+ clock-output-names = "clk_nandc0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[6:5]: reserved */
+
+ clk_nandc0: clk_nandc0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <7 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_nandc0";
+ #clock-cells = <0>;
+ };
+
+ clk_nandc1_div: clk_nandc1_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_nandc1>;
+ clock-output-names = "clk_nandc1";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[14:13]: reserved */
+
+ clk_nandc1: clk_nandc1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_nandc1";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con39: sel-con@00fc {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00fc 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_spi2_div: clk_spi2_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_spi2>;
+ clock-output-names = "clk_spi2";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_spi2: clk_spi2_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <7 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_spi2";
+ #clock-cells = <0>;
+ };
+
+ aclk_hevc_div: aclk_hevc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&aclk_hevc>;
+ clock-output-names = "aclk_hevc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[13]: reserved */
+
+ aclk_hevc: aclk_hevc_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "aclk_hevc";
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con40: sel-con@0100 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0100 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spdif_8ch_pll_div: spdif_8ch_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_spdif_pll>;
+ clock-output-names = "spdif_8ch_pll_div";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[7]: reserved */
+
+ clk_spdif_8ch: spdif_8ch_clk_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&spdif_8ch_pll_div>, <&spdif_8ch_frac>, <&xin12m>;
+ clock-output-names = "clk_spdif_8ch";
+ #clock-cells = <0>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* reg[11:10]: reserved */
+
+ hclk_hevc: hclk_hevc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <12 2>;
+ clocks = <&aclk_hevc>;
+ clock-output-names = "hclk_hevc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* reg[15:14]: reserved */
+ };
+
+ clk_sel_con41: sel-con@0104 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0104 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spdif_8ch_frac: spdif_8ch_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&spdif_8ch_pll_div>;
+ clock-output-names = "spdif_8ch_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con42: sel-con@0108 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0108 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_hevc_cabac_div: clk_hevc_cabac_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_hevc_cabac>;
+ clock-output-names = "clk_hevc_cabac";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[5]: reserved */
+
+ clk_hevc_cabac: clk_hevc_cabac_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "clk_hevc_cabac";
+ #clock-cells = <0>;
+ };
+
+ clk_hevc_core_div: clk_hevc_core_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_hevc_core>;
+ clock-output-names = "clk_hevc_core";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* reg[13]: reserved */
+
+ clk_hevc_core: clk_hevc_core_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clock-output-names = "clk_hevc_core";
+ #clock-cells = <0>;
+ };
+ };
+
+ };
+
+
+ /* Gate control regs */
+ clk_gate_cons {
+ compatible = "rockchip,rk-gate-cons";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges ;
+
+ clk_gates0: gate-clk@0160 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0160 0x4>;
+ clocks =
+ <&dummy>, <&clk_apll>,
+ <&clk_gpll>, <&aclk_bus>,
+
+ <&hclk_bus>, <&pclk_bus>,
+ <&dummy>, <&aclk_bus>,
+
+ <&clk_dpll>, <&clk_gpll>,
+ <&clk_gpll>, <&clk_cpll>,
+
+ <&xin24m>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "reserved", "core_apll",
+ "clk_arm_gpll", "g_aclk_bus",
+
+ "hclk_bus", "pclk_bus",
+ "reserved", "aclk_bus_2pmu",
+
+ "reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
+ "clk_bus_gpll", "clk_bus_cpll",
+
+ "clk_acc_efuse", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates1: gate-clk@0164 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0164 0x4>;
+ clocks =
+ <&xin24m>, <&xin24m>,
+ <&xin24m>, <&xin24m>,
+
+ <&xin24m>, <&xin24m>,
+ <&dummy>, <&dummy>,
+
+ <&clk_uart0_pll>, <&uart0_frac>,
+ <&clk_uart1_div>, <&uart1_frac>,
+
+ <&clk_uart2_div>, <&uart2_frac>,
+ <&clk_uart3_div>, <&uart3_frac>;
+
+ clock-output-names =
+ "clk_timer0", "clk_timer1",
+ "clk_timer2", "clk_timer3",
+
+ "clk_timer4", "clk_timer5",
+ "reserved", "reserved",
+
+ "clk_uart0_pll", "uart0_frac",
+ "clk_uart1_div", "uart1_frac",
+
+ "clk_uart2_div", "uart2_frac",
+ "clk_uart3_div", "uart3_frac";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates2: gate-clk@0168 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0168 0x4>;
+ clocks =
+ <&aclk_peri>, <&aclk_peri>,
+ <&hclk_peri>, <&pclk_peri>,
+
+ <&dummy>, <&clk_mac_pll>,
+ <&clk_hsadc_pll>, <&clk_tsadc>,
+
+ <&clk_saradc>, <&clk_spi0>,
+ <&clk_spi1>, <&clk_spi2>,
+
+ <&clk_uart4_div>, <&uart4_frac>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "aclk_peri", "g_aclk_periph",
+ "hclk_peri", "pclk_peri",
+
+ "reserved", "clk_mac_pll",
+ "clk_hsadc_pll", "clk_tsadc",
+
+ "clk_saradc", "clk_spi0",
+ "clk_spi1", "clk_spi2",
+
+ "clk_uart4_div", "uart4_frac",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates3: gate-clk@016c {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x016c 0x4>;
+ clocks =
+ <&aclk_vio0>, <&dclk_lcdc0>,
+ <&aclk_vio1>, <&dclk_lcdc1>,
+
+ <&clk_rga>, <&aclk_rga>,
+ <&clk_hsicphy_480m>, <&clk_cif_pll>,
+
+ <&dummy>, <&clk_vepu>,
+ <&dummy>, <&clk_vdpu>,
+
+ <&clk_edp_24m>, <&clk_edp>,
+ <&clk_isp>, <&clk_isp_jpe>;
+
+ clock-output-names =
+ "aclk_vio0", "dclk_lcdc0",
+ "aclk_vio1", "dclk_lcdc1",
+
+ "clk_rga", "aclk_rga",
+ "clk_hsicphy_480m", "clk_cif_pll",
+
+ /*Not use hclk_vpu_gate tmp, fixme*/
+ "reserved", "clk_vepu",
+ "reserved", "clk_vdpu",
+
+ "clk_edp_24m", "clk_edp",
+ "clk_isp", "clk_isp_jpe";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates4: gate-clk@0170 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0170 0x4>;
+ clocks =
+ <&clk_i2s0_out>, <&clk_i2s_pll>,
+ <&i2s0_frac>, <&clk_i2s0>,
+
+ <&spdif_pll_div>, <&spdif_frac>,
+ <&clk_spdif>, <&spdif_8ch_pll_div>,
+
+ <&spdif_8ch_frac>, <&clk_spdif_8ch>,
+ <&clk_tsp>, <&clk_tspout>,
+
+ <&clk_ddr>, <&clk_ddr>,
+ <&jtag_clkin>, <&dummy>;
+
+ clock-output-names =
+ "clk_i2s0_out", "clk_i2s_pll",
+ "i2s0_frac", "g_clk_i2s0",
+
+ "spdif_pll_div", "spdif_frac",
+ "clk_spdif", "spdif_8ch_pll_div",
+
+ "spdif_8ch_frac", "clk_spdif_8ch",
+ "clk_tsp", "clk_tspout",
+
+ /* Not use these ddr gates */
+ "reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
+ "clk_jtag", "reserved"; /*"testclk_gate_en";*/
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates5: gate-clk@0174 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0174 0x4>;
+ clocks =
+ <&clk_mac>, <&clk_mac>,
+ <&clk_mac>, <&clk_mac>,
+
+ <&clk_crypto>, <&clk_nandc0>,
+ <&clk_nandc1>, <&clk_gpu>,
+
+ <&pclk_pd_pmu>, <&dummy>,
+ <&dummy>, <&xin32k>,
+
+ <&xin24m>, <&xin24m>,
+ <&usbphy_480m>, <&dummy>;
+
+ clock-output-names =
+ "g_clk_mac_rx", "g_clk_mac_tx",
+ "g_clk_mac_ref", "g_clk_mac_refout",
+
+ "clk_crypto", "clk_nandc0",
+ "clk_nandc1", "clk_gpu",
+
+ "pclk_pd_pmu", "g_clk_pvtm_core",
+ "g_clk_pvtm_gpu", "g_hdmi_cec_clk",
+
+ "g_hdmi_hdcp_clk", "g_ps2c_clk",
+ "usbphy_480m", "g_clk_mipidsi_24m";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates6: gate-clk@0178 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0178 0x4>;
+ clocks =
+ <&hclk_peri>, <&pclk_peri>,
+ <&aclk_peri>, <&aclk_peri>,
+
+ <&pclk_peri>, <&pclk_peri>,
+ <&pclk_peri>, <&pclk_peri>,
+
+ <&pclk_peri>, <&pclk_peri>,
+ <&dummy>, <&pclk_peri>,
+
+ <&pclk_peri>, <&pclk_peri>,
+ <&pclk_peri>, <&pclk_peri>;
+
+ clock-output-names =
+ "g_hclk_peri_matrix", "g_pclk_peri_axi_matrix",
+ "g_aclk_peri_axi_matrix", "g_aclk_dmac2",
+
+ "g_pclk_spi0", "g_pclk_spi1",
+ "g_pclk_spi2", "g_pclk_ps2c",
+
+ "g_pclk_uart0", "g_pclk_uart1",
+ "reserved", "g_pclk_uart2",
+
+ "g_pclk_uart3", "g_pclk_i2c2",
+ "g_pclk_i2c3", "g_pclk_i2c4";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates7: gate-clk@017c {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x017c 0x4>;
+ clocks =
+ <&pclk_peri>, <&pclk_peri>,
+ <&pclk_peri>, <&pclk_peri>,
+
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&hclk_peri>,
+
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&aclk_peri>,
+
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&hclk_peri>;
+
+ clock-output-names =
+ "g_pclk_i2c5", "g_pclk_saradc",
+ "g_pclk_tsadc", "g_pclk_sim",
+
+ "g_hclk_otg0", "g_pmu_hclk_otg0",
+ "g_hclk_host0", "g_hclk_host1",
+
+ "g_hclk_hsic", "g_hclk_usb_peri",
+ "g_hclk_peri_ahb_arbi", "g_aclk_peri_niu",
+
+ "g_hclk_emem_peri", "g_hclk_mem_peri",
+ "g_hclk_nandc0", "g_hclk_nandc1";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates8: gate-clk@0180 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0180 0x4>;
+ clocks =
+ <&aclk_peri>, <&pclk_peri>,
+ <&aclk_peri>, <&hclk_peri>,
+
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&hclk_peri>,
+
+ <&hclk_peri>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&aclk_peri>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_aclk_gmac", "g_pclk_gmac",
+ "g_hclk_gps", "g_hclk_sdmmc",
+
+ "g_hclk_sdio0", "g_hclk_sdio1",
+ "g_hclk_emmc", "g_hclk_hsadc",
+
+ "g_hclk_tsp", "g_clk_hsadc_0_tsp",
+ "g_clk_hsadc_1_tsp", "g_clk_27m_tsp",
+
+ "g_aclk_peri_mmu", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates9: gate-clk@0184 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0184 0x4>;
+ clocks =
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates10: gate-clk@0188 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0188 0x4>;
+ clocks =
+ <&pclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>,
+
+ <&aclk_bus>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&hclk_bus>, <&hclk_bus>,
+ <&hclk_bus>, <&hclk_bus>,
+
+ <&aclk_bus>, <&aclk_bus>,
+ <&pclk_bus>, <&pclk_bus>;
+
+ clock-output-names =
+ "g_pclk_pwm", "g_pclk_timer",
+ "g_pclk_i2c0", "g_pclk_i2c1",
+
+ "g_aclk_intmem", "g_clk_intmem0",
+ "g_clk_intmem1", "g_clk_intmem2",
+
+ "g_hclk_i2s", "g_hclk_rom",
+ "g_hclk_spdif", "g_hclk_spdif_8ch",
+
+ "g_aclk_dmac1", "g_aclk_strc_sys",
+ "g_pclk_ddrupctl0", "g_pclk_publ0";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates11: gate-clk@018c {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x018c 0x4>;
+ clocks =
+ <&pclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>,
+
+ <&dummy>, <&dummy>,
+ <&aclk_bus>, <&hclk_bus>,
+
+ <&aclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_pclk_ddrupctl1", "g_pclk_publ1",
+ "g_pclk_efuse_1024", "g_pclk_tzpc",
+
+ "reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
+ "g_aclk_crypto", "g_hclk_crypto",
+
+ "g_aclk_ccp", "g_pclk_uart2",
+ "g_pclk_efuse_256", "g_pclk_rkpwm",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates12: gate-clk@0190 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0190 0x4>;
+ clocks =
+ <&clk_core0>, <&clk_core1>,
+ <&clk_core2>, <&clk_core3>,
+
+ <&clk_l2ram>, <&aclk_core_m0>,
+ <&aclk_core_mp>, <&atclk_core>,
+
+ <&pclk_dbg_src>, <&clk_gates12 8>,
+ <&clk_gates12 8>, <&clk_gates12 8>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "clk_core0", "clk_core1",
+ "clk_core2", "clk_core3",
+
+ "clk_l2ram", "aclk_core_m0",
+ "aclk_core_mp", "atclk_core",
+
+ "pclk_dbg_src", "g_dbg_core_clk",
+ "g_cs_dbg_clk", "g_pclk_core_niu",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates13: gate-clk@0194 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0194 0x4>;
+ clocks =
+ <&clk_sdmmc0>, <&clk_sdio0>,
+ <&clk_sdio1>, <&clk_emmc>,
+
+ <&xin24m>, <&xin24m>,
+ <&xin24m>, <&xin32k>,
+
+ <&aclk_bus_src>, <&xin12m>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&aclk_hevc>,
+ <&clk_hevc_cabac>, <&clk_hevc_core>;
+
+ clock-output-names =
+ "clk_sdmmc0", "clk_sdio0",
+ "clk_sdio1", "clk_emmc",
+
+ "clk_otgphy0", "clk_otgphy1",
+ "clk_otgphy2", "clk_otg_adp",
+
+ "g_clk_c2c_host", "g_clk_hsic_12m",
+ "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
+
+ "g_clk_wifi", "aclk_hevc",
+ "clk_hevc_cabac", "clk_hevc_core";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates14: gate-clk@0198 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0198 0x4>;
+ clocks =
+ <&dummy>, <&pclk_pd_alive>,
+ <&pclk_pd_alive>, <&pclk_pd_alive>,
+
+ <&pclk_pd_alive>, <&pclk_pd_alive>,
+ <&pclk_pd_alive>, <&pclk_pd_alive>,
+
+ <&pclk_pd_alive>, <&dummy>,
+ <&dummy>, <&pclk_pd_alive>,
+
+ <&pclk_pd_alive>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "reserved", "g_pclk_gpio1",
+ "g_pclk_gpio2", "g_pclk_gpio3",
+
+ "g_pclk_gpio4", "g_pclk_gpio5",
+ "g_pclk_gpio6", "g_pclk_gpio7",
+
+ "g_pclk_gpio8", "reserved",
+ "reserved", "g_pclk_grf",
+
+ "g_pclk_alive_niu", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates15: gate-clk@019c {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x019c 0x4>;
+ clocks =
+ <&aclk_rga>, <&hclk_vio>,
+ <&aclk_vio0>, <&hclk_vio>,
+
+ <&dummy>, <&aclk_vio0>,
+ <&hclk_vio>, <&aclk_vio1>,
+
+ <&hclk_vio>, <&hclk_vio>,
+ <&hclk_vio>, <&aclk_vio0>,
+
+ <&aclk_vio1>, <&aclk_rga>,
+ <&aclk_vio0>, <&hclk_vio>;
+
+ clock-output-names =
+ "g_aclk_rga", "g_hclk_rga",
+ "g_aclk_iep", "g_hclk_iep",
+
+ "g_aclk_lcdc_iep", "g_aclk_lcdc0",
+ "g_hclk_lcdc0", "g_aclk_lcdc1",
+
+ "g_hclk_lcdc1", "g_hclk_vio_ahb_arbi",
+ "g_hclk_vio_niu", "g_aclk_vio0_niu",
+
+ "g_aclk_vio1_niu", "g_aclk_vio2_niu",
+ "g_aclk_vip", "g_hclk_vip";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates16: gate-clk@01a0 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x01a0 0x4>;
+ clocks =
+ <&pclkin_cif>, <&hclk_vio>,
+ <&aclk_vio1>, <&pclkin_isp>,
+
+ <&hclk_vio>, <&hclk_vio>,
+ <&hclk_vio>, <&hclk_vio>,
+
+ <&hclk_vio>, <&hclk_vio>,
+ <&hclk_vio>, <&hclk_vio>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_pclkin_cif", "g_hclk_isp",
+ "g_aclk_isp", "g_pclkin_isp",
+
+ "g_pclk_mipi_dsi0", "g_pclk_mipi_dsi1",
+ "g_pclk_mipi_csi", "g_pclk_lvds_phy",
+
+ "g_pclk_edp_ctrl", "g_pclk_hdmi_ctrl",
+ "g_hclk_vio2_h2p", "g_pclk_vio2_h2p",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates17: gate-clk@01a4 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x01a4 0x4>;
+ clocks =
+ <&pclk_pd_pmu>, <&pclk_pd_pmu>,
+ <&pclk_pd_pmu>, <&pclk_pd_pmu>,
+
+ <&pclk_pd_pmu>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_pclk_pmu", "g_pclk_intmem1",
+ "g_pclk_pmu_niu", "g_pclk_sgrf",
+
+ "g_pclk_gpio0", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates18: gate-clk@01a8 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x01a8 0x4>;
+ clocks =
+ <&clk_gpu>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_aclk_gpu", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ };
+ };
+ };
};
projects / firefly-linux-kernel-4.4.55.git / commitdiff