arm: zynq: timer: Align columns

Aligning the columns in a block of #defines, so that the values
are starting in the same colum on every line.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>

diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 80bf4742fe376adadd44af5586520b4500115c70..4b81ae1153d360d3d026ad9c7f95f2c429e946ec 100644 (file)
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -35,9 +35,9 @@
  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  * and use same offsets for Timer 2
  */
-#define XTTCPS_CLK_CNTRL_OFFSET        0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET        0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET        0x18 /* Counter Value Reg, RO */
+#define XTTCPS_CLK_CNTRL_OFFSET                0x00 /* Clock Control Reg, RW */
+#define XTTCPS_CNT_CNTRL_OFFSET                0x0C /* Counter Control Reg, RW */
+#define XTTCPS_COUNT_VAL_OFFSET                0x18 /* Counter Value Reg, RO */
 #define XTTCPS_INTR_VAL_OFFSET         0x24 /* Interval Count Reg, RW */
 #define XTTCPS_ISR_OFFSET              0x54 /* Interrupt Status Reg, RO */
 #define XTTCPS_IER_OFFSET              0x60 /* Interrupt Enable Reg, RW */