cl::init(false), cl::Hidden);
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
- bool isThumb)
+ bool isT)
: ARMArchVersion(V4T)
, ARMFPUType(None)
, UseNEONForSinglePrecisionFP(UseNEONFP)
- , IsThumb(isThumb)
+ , IsThumb(isT)
, ThumbMode(Thumb1)
, PostRAScheduler(false)
, IsR9Reserved(ReserveR9)
if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+ if (!isThumb() || hasThumb2())
+ PostRAScheduler = true;
+
// Set CPU specific features.
if (CPUString == "cortex-a8") {
- PostRAScheduler = true;
// On Cortext-a8, it's faster to perform some single-precision FP
// operations with NEON instructions.
if (UseNEONFP.getPosition() == 0)
define i64 @t(i64 %a) nounwind readonly {
entry:
-;V6: ldrd r2, [r2]
+;V6: ldrd r2, [r2]
-;V5: ldr r3, [r2]
-;V5-NEXT: ldr r2, [r2, #+4]
+;V5: ldr r3, [r2]
+;V5: ldr r2, [r2, #+4]
-;EABI: ldr r3, [r2]
-;EABI-NEXT: ldr r2, [r2, #+4]
+;EABI: ldr r3, [r2]
+;EABI: ldr r2, [r2, #+4]
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4