Enable post-alloc scheduling for all ARM variants except for Thumb1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 698e5e2115e58c3648d9bde16104d3beac764fbd..e4396d01fedc5712e8811cf8542e20c7c41814a5 100644 (file)
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -27,11 +27,11 @@ UseNEONFP("arm-use-neon-fp",
           cl::init(false), cl::Hidden);
 
 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
-                           bool isThumb)
+                           bool isT)
   : ARMArchVersion(V4T)
   , ARMFPUType(None)
   , UseNEONForSinglePrecisionFP(UseNEONFP)
-  , IsThumb(isThumb)
+  , IsThumb(isT)
   , ThumbMode(Thumb1)
   , PostRAScheduler(false)
   , IsR9Reserved(ReserveR9)
@@ -98,9 +98,11 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
   if (isTargetDarwin())
     IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
 
+  if (!isThumb() || hasThumb2())
+    PostRAScheduler = true;
+
   // Set CPU specific features.
   if (CPUString == "cortex-a8") {
-    PostRAScheduler = true;
     // On Cortext-a8, it's faster to perform some single-precision FP
     // operations with NEON instructions.
     if (UseNEONFP.getPosition() == 0)

diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll
index 8f7ae55c6eaf177ecb66a81edba68d948afbe4ec..c366e2dca5fb0ebfe312fdc3244f1510d44e5253 100644 (file)
--- a/test/CodeGen/ARM/ldrd.ll
+++ b/test/CodeGen/ARM/ldrd.ll
@@ -7,13 +7,13 @@
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-;V6:      ldrd r2, [r2]
+;V6:   ldrd r2, [r2]
 
-;V5:      ldr r3, [r2]
-;V5-NEXT: ldr r2, [r2, #+4]
+;V5:   ldr r3, [r2]
+;V5:   ldr r2, [r2, #+4]
 
-;EABI:      ldr r3, [r2]
-;EABI-NEXT: ldr r2, [r2, #+4]
+;EABI: ldr r3, [r2]
+;EABI: ldr r2, [r2, #+4]
 
        %0 = load i64** @b, align 4
        %1 = load i64* %0, align 4