timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
};
};
- nandc: nandc@0xff400000 {
+ nandc: nandc@10500000 {
compatible = "rockchip,rk-nandc";
- reg = <0xff400000 0x4000>;
+ reg = <0x10500000 0x4000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ nandc_id = <0>;
clocks = <&clk_nandc>, <&clk_gates5 9>;
clock-names = "clk_nandc", "hclk_nandc";
};
rockchip_soc_id = ROCKCHIP_SOC_RK3036;
iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
-
+ debug_ll_io_init();
/* enable timer5 for core */
writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
dsb();
dsb();
}
+static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on)
+{
+ return 0;
+}
+
+static bool rk3036_pmu_power_domain_is_on(enum pmu_power_domain pd)
+{
+ return 0;
+}
+
+static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
+{
+ return 0;
+}
+
static void __init rk3036_dt_init_timer(void)
{
+ rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
+ rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
+ rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
clocksource_of_init();
}