[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.

The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213850 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ccef6c3b6cbf0d94c9f5d8b5c47baa4e7aa2303e..e34282bfca7fa87292e5fb181dc462f548b9ed99 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5732,6 +5732,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
   case ARM::STR_PRE_REG:
   case ARM::STR_POST_IMM:
   case ARM::STR_POST_REG:
+  case ARM::STRH_PRE:
+  case ARM::STRH_POST:
   case ARM::STRB_PRE_IMM:
   case ARM::STRB_PRE_REG:
   case ARM::STRB_POST_IMM:

diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index 25eb6f227a63f3e952600de46717ccb975fd2024..83af10d2091d4bc526461b957e5119976c137145 100644 (file)
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -496,6 +496,10 @@ foo2:
         str r0, [r0, r1]!
         str r0, [r0], #4
         str r0, [r0], r1
+        strh r0, [r0, #2]!
+        strh r0, [r0, r1]!
+        strh r0, [r0], #2
+        strh r0, [r0], r1
         strb r0, [r0, #1]!
         strb r0, [r0, r1]!
         strb r0, [r0], #1
@@ -513,6 +517,18 @@ foo2:
 @ CHECK-ERRORS: str r0, [r0], r1
 @ CHECK-ERRORS:         ^
 @ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0, #2]!
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0, r1]!
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0], #2
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0], r1
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
 @ CHECK-ERRORS: strb r0, [r0, #1]!
 @ CHECK-ERRORS:          ^
 @ CHECK-ERRORS: error: source register and base register can't be identical