clk: rockchip: fix pll_clk_get_best_set() for rk3188plus type pll

When selecting a best setting for rk3188plus type pll, consider a
larger NO first(means larger VCO freq), and a smaller NR later.

Signed-off-by: dkl <dkl@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 40a2f9873e95b9508de5d3b7416711b6402431b0..09b627e7a170db9b1f74423195c01082aa1cd7d2 100755 (executable)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1025,7 +1025,7 @@ static int pll_clk_get_best_set(unsigned long fin_hz, unsigned long fout_hz,
                       //printk("_PLL_SET_CLKS(%lu,\t%d,\t%d,\t%d),\n",fout_hz/KHZ,nr,nf,no);
 
                       /* select the best from all available PLL settings */
-                      if((nr < nr_out) || ((nr == nr_out)&&(no > no_out)))
+                      if ((no > no_out) || ((no == no_out) && (nr < nr_out)))
                       {
                               nr_out = nr;
                               nf_out = nf;