drm/nouveau/imem: switch to device pri macros

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
index abc41c0a4ad83748b63f3053f1f8e7bb929b74f2..e2e400e35bc8bd6ac193067fe141dbc78b01be87 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
@@ -107,6 +107,7 @@ gk20a_instobj_rd32(struct nvkm_object *object, u64 offset)
 {
        struct gk20a_instmem *imem = (void *)nvkm_instmem(object);
        struct gk20a_instobj *node = (void *)object;
+       struct nvkm_device *device = imem->base.subdev.device;
        unsigned long flags;
        u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
        u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
@@ -114,10 +115,10 @@ gk20a_instobj_rd32(struct nvkm_object *object, u64 offset)
 
        spin_lock_irqsave(&imem->lock, flags);
        if (unlikely(imem->addr != base)) {
-               nv_wr32(imem, 0x001700, base >> 16);
+               nvkm_wr32(device, 0x001700, base >> 16);
                imem->addr = base;
        }
-       data = nv_rd32(imem, 0x700000 + addr);
+       data = nvkm_rd32(device, 0x700000 + addr);
        spin_unlock_irqrestore(&imem->lock, flags);
        return data;
 }
@@ -127,16 +128,17 @@ gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
 {
        struct gk20a_instmem *imem = (void *)nvkm_instmem(object);
        struct gk20a_instobj *node = (void *)object;
+       struct nvkm_device *device = imem->base.subdev.device;
        unsigned long flags;
        u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
        u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
 
        spin_lock_irqsave(&imem->lock, flags);
        if (unlikely(imem->addr != base)) {
-               nv_wr32(imem, 0x001700, base >> 16);
+               nvkm_wr32(device, 0x001700, base >> 16);
                imem->addr = base;
        }
-       nv_wr32(imem, 0x700000 + addr, data);
+       nvkm_wr32(device, 0x700000 + addr, data);
        spin_unlock_irqrestore(&imem->lock, flags);
 }
 

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
index 23084f18199ec336de15214742f735cccfbb1247..6410cc1fd419c964f298c86ac16146ae821b2a79 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
@@ -105,13 +105,15 @@ nv04_instobj_oclass = {
 static u32
 nv04_instmem_rd32(struct nvkm_object *object, u64 addr)
 {
-       return nv_rd32(object, 0x700000 + addr);
+       struct nvkm_instmem *imem = (void *)object;
+       return nvkm_rd32(imem->subdev.device, 0x700000 + addr);
 }
 
 static void
 nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
 {
-       return nv_wr32(object, 0x700000 + addr, data);
+       struct nvkm_instmem *imem = (void *)object;
+       nvkm_wr32(imem->subdev.device, 0x700000 + addr, data);
 }
 
 void

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
index d6827b377bd956ce2f70d8cb1e8db3ac96f2e1cb..fe00881bda65021a250b183f051895875014bdf6 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
@@ -75,7 +75,7 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
         * to fit graphics contexts for every channel, the magics come
         * from engine/gr/nv40.c
         */
-       vs = hweight8((nv_rd32(imem, 0x001540) & 0x0000ff00) >> 8);
+       vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8);
        if      (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs;
        else if (device->chipset  < 0x43) imem->base.reserved = 0x4f00 * vs;
        else if (nv44_gr_class(imem))  imem->base.reserved = 0x4980 * vs;

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
index 6c83c5797e32294978450d3891cc7b0b44876054..339dd19e0e4516d42e011376884c5d0e6a07193d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
@@ -45,6 +45,7 @@ nv50_instobj_rd32(struct nvkm_object *object, u64 offset)
 {
        struct nv50_instmem *imem = (void *)nvkm_instmem(object);
        struct nv50_instobj *node = (void *)object;
+       struct nvkm_device *device = imem->base.subdev.device;
        unsigned long flags;
        u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
        u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
@@ -52,10 +53,10 @@ nv50_instobj_rd32(struct nvkm_object *object, u64 offset)
 
        spin_lock_irqsave(&imem->lock, flags);
        if (unlikely(imem->addr != base)) {
-               nv_wr32(imem, 0x001700, base >> 16);
+               nvkm_wr32(device, 0x001700, base >> 16);
                imem->addr = base;
        }
-       data = nv_rd32(imem, 0x700000 + addr);
+       data = nvkm_rd32(device, 0x700000 + addr);
        spin_unlock_irqrestore(&imem->lock, flags);
        return data;
 }
@@ -65,16 +66,17 @@ nv50_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
 {
        struct nv50_instmem *imem = (void *)nvkm_instmem(object);
        struct nv50_instobj *node = (void *)object;
+       struct nvkm_device *device = imem->base.subdev.device;
        unsigned long flags;
        u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
        u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
 
        spin_lock_irqsave(&imem->lock, flags);
        if (unlikely(imem->addr != base)) {
-               nv_wr32(imem, 0x001700, base >> 16);
+               nvkm_wr32(device, 0x001700, base >> 16);
                imem->addr = base;
        }
-       nv_wr32(imem, 0x700000 + addr, data);
+       nvkm_wr32(device, 0x700000 + addr, data);
        spin_unlock_irqrestore(&imem->lock, flags);
 }