=head1 CODE GENERATION OPTIONS
-=over
+=over 4
=item B<-code-model>=I<model>
Choose the code model from:
-=over 2
+=back
+
+=over 8
=item I<default>: Target default code model
=back
+=over 4
+
=item B<-disable-post-RA-scheduler>
Disable scheduling after register allocation.
Instruction schedulers available (before register allocation):
-=over 2
+=back
+
+=over 8
=item I<=default>: Best scheduler for the target
=back
+=over 4
+
=item B<-regalloc>=I<allocator>
Register allocator to use: (default = linearscan)
-=over 2
+=back
+
+=over 8
=item I<=bigblock>: Big-block register allocator
=back
+=over 4
+
=item B<-relocation-model>=I<model>
Choose relocation model from:
-=over 2
+=back
+
+=over 8
=item I<=default>: Target default relocation model
=back
+=over 4
+
=item B<-spiller>
Spiller to use: (default: local)
-=over 2
+=back
+
+=over 8
=item I<=simple>: simple spiller
=back
+=over 4
+
=item B<-x86-asm-syntax>=I<syntax>
Choose style of code to emit from X86 backend:
-=over 2
+=back
+
+=over 8
=item I<=att>: Emit AT&T-style assembly
=back
-=back
-
=head1 EXIT STATUS
If B<lli> fails to load the program, it will exit with an exit code of 1.