rk3288: set RK3288_LIMIT_PLL_VIO1 to 410MHZ

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 4e7aef47321ce5fc6cd4c2094411d8e01b45676d..604a94f8b91673e2141df58fbe76b5e688bf4af8 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -616,7 +616,7 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc0 = {
        .recalc_rate    = clk_divider_recalc_rate,
 };
 
-#define RK3288_LIMIT_PLL_VIO1 (348*MHZ)
+#define RK3288_LIMIT_PLL_VIO1 (410*MHZ)
 
 static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long rate,
                unsigned long *best_parent_rate,