mn10300: add cc clobbers to asm statements
authorMark Salter <msalter@redhat.com>
Fri, 8 Jan 2010 22:43:16 +0000 (14:43 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Jan 2010 17:34:10 +0000 (09:34 -0800)
gcc 4.2.1 for MN10300 is more agressive than the older gcc in
reordering/moving other insns between an insn that sets flags and an insn
that uses those flags.  This leads to trouble with asm statements which
are missing an explicit "cc" clobber.  This patch adds the explicit "cc"
clobber to asm statements which do indeed clobber the condition flags.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arch/mn10300/include/asm/bitops.h
arch/mn10300/include/asm/div64.h
arch/mn10300/include/asm/system.h
arch/mn10300/include/asm/tlbflush.h
arch/mn10300/include/asm/uaccess.h
arch/mn10300/kernel/mn10300-serial.c
arch/mn10300/lib/checksum.c
arch/mn10300/lib/delay.c
arch/mn10300/lib/usercopy.c
arch/mn10300/mm/misalignment.c

index 0b610f482abb9fbe0622e9b6758cbc758e046de3..f49ac49e09adc079adaabdd9893258ae9b795b7f 100644 (file)
@@ -165,7 +165,7 @@ static inline __attribute__((const))
 unsigned long __ffs(unsigned long x)
 {
        int bit;
-       asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x));
+       asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x) : "cc");
        return bit;
 }
 
@@ -177,7 +177,7 @@ static inline __attribute__((const))
 int __ilog2_u32(u32 n)
 {
        int bit;
-       asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n));
+       asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n) : "cc");
        return bit;
 }
 
index 3a8329b3e8694493c6b018eea7820873d04110f8..34dcb8e68309e0331b12d5ce2051a05da04e4c3f 100644 (file)
@@ -72,6 +72,7 @@ unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div)
                                         * MDR = MDR:val%div */
            : "=r"(result)
            : "0"(val), "ir"(mult), "r"(div)
+           : "cc"
            );
 
        return result;
@@ -92,6 +93,7 @@ signed __muldiv64s(signed val, signed mult, signed div)
                                         * MDR = MDR:val%div */
            : "=r"(result)
            : "0"(val), "ir"(mult), "r"(div)
+           : "cc"
            );
 
        return result;
index 8214fb7e7fe4747a5cd6962201efeefa2d00e094..3636c054dcd526202a3028c389c8515a450ffa98 100644 (file)
@@ -143,6 +143,7 @@ do {                                                                        \
                "       mov     %0,epsw         \n"                     \
                : "=&d"(tmp)                                            \
                : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw)        \
+               : "cc"                                                  \
                );                                                      \
 } while (0)
 
index e0239865abcbe28946e82f6fa0c5d5900a42464b..1a7e29281c5d0642ca0e66b91ca054f8353989b1 100644 (file)
@@ -22,7 +22,7 @@ do {                                                          \
                 "      mov %0,%1               \n"             \
                 : "=d"(w)                                      \
                 : "m"(MMUCTR), "i"(MMUCTR_IIV|MMUCTR_DIV)      \
-                : "memory"                                     \
+                : "cc", "memory"                               \
                 );                                             \
 } while (0)
 
index 167e10ff06d99ddb57175117e552bb9b4835faa1..197a7af3dd8aeaa7014df5856877de3f0924ee71 100644 (file)
@@ -316,7 +316,7 @@ do {                                                                        \
                        "       .previous\n"                            \
                        : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\
                        : "0"(__from), "1"(__to), "2"(size)             \
-                       : "memory");                                    \
+                       : "cc", "memory");                              \
        }                                                               \
 } while (0)
 
@@ -352,7 +352,7 @@ do {                                                                        \
                        "       .previous\n"                            \
                        : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\
                        : "0"(__from), "1"(__to), "2"(size)             \
-                       : "memory");                                    \
+                       : "cc", "memory");                              \
        }                                                               \
 } while (0)
 
index 229b710fc5d5a65c0c6ed20f269fbb60dc709e31..ef34d5a0f8bd35c8d88cf1e46c54455d0cc97b31 100644 (file)
@@ -380,7 +380,8 @@ static int mask_test_and_clear(volatile u8 *ptr, u8 mask)
        u32 epsw;
        asm volatile("  bclr    %1,(%2)         \n"
                     "  mov     epsw,%0         \n"
-                    : "=d"(epsw) : "d"(mask), "a"(ptr));
+                    : "=d"(epsw) : "d"(mask), "a"(ptr)
+                    : "cc", "memory");
        return !(epsw & EPSW_FLAG_Z);
 }
 
index 274f29ec33c1de3d0e9070bddad0570a07716056..b6580f5d89eef78aa00a9ad0e68ab76002af6704 100644 (file)
@@ -22,6 +22,7 @@ static inline unsigned short from32to16(__wsum sum)
            "   addc    0xffff,%0       \n"
            : "=r" (sum)
            : "r" (sum << 16), "0" (sum & 0xffff0000)
+           : "cc"
            );
        return sum >> 16;
 }
index cce66bc0822d71c1ca41f4ab91d441df9b355b62..fdf6f710f94ec388f8c230afc8bff6139cc6295b 100644 (file)
@@ -28,7 +28,8 @@ void __delay(unsigned long loops)
                "2:     add     -1,%0   \n"
                "       bne     2b      \n"
                : "=&d" (d0)
-               : "0" (loops));
+               : "0" (loops)
+               : "cc");
 }
 EXPORT_SYMBOL(__delay);
 
index a75b203059c1b358434f616ae7b3a7243cb65d33..7826e6c364e74f0075e43081e5db367062baef30 100644 (file)
@@ -62,7 +62,7 @@ do {                                                          \
                "       .previous"                              \
                :"=&r"(res), "=r"(count), "=&r"(w)              \
                :"i"(-EFAULT), "1"(count), "a"(src), "a"(dst)   \
-               :"memory");                                     \
+               : "memory", "cc");                                      \
 } while (0)
 
 long
@@ -109,7 +109,7 @@ do {                                                \
                ".previous\n"                   \
                : "+r"(size), "=&r"(w)          \
                : "a"(addr), "d"(0)             \
-               : "memory");                    \
+               : "memory", "cc");              \
 } while (0)
 
 unsigned long
@@ -161,6 +161,6 @@ long strnlen_user(const char *s, long n)
                ".previous\n"
                :"=d"(res), "=&r"(w)
                :"0"(0), "a"(s), "r"(n)
-               :"memory");
+               : "memory", "cc");
        return res;
 }
index 30016251f658507ec5a6501c35028dd74be22716..6dffbf97ac2601d40ceb91a2e4a5116fd1bceeb8 100644 (file)
@@ -633,13 +633,13 @@ static int misalignment_addr(unsigned long *registers, unsigned long sp,
                        goto displace_or_inc;
                case SD24:
                        tmp = disp << 8;
-                       asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
+                       asm("asr 8,%0" : "=r"(tmp) : "0"(tmp) : "cc");
                        disp = (long) tmp;
                        goto displace_or_inc;
                case SIMM4_2:
                        tmp = opcode >> 4 & 0x0f;
                        tmp <<= 28;
-                       asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
+                       asm("asr 28,%0" : "=r"(tmp) : "0"(tmp) : "cc");
                        disp = (long) tmp;
                        goto displace_or_inc;
                case IMM8: