ENTRY(rk30_sram_secondary_startup)
ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
- ldr pc, 1f
1: .long rk30_secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
ENDPROC(rk30_sram_secondary_startup)
/*
* SRAM memory whereabouts
*/
-#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0100)
+#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0010)
#define SRAM_CODE_END (RK30_IMEM_BASE + 0x2FFF)
#define SRAM_DATA_OFFSET (RK30_IMEM_BASE + 0x3000)
#define SRAM_DATA_END (RK30_IMEM_BASE + 0x3FFF)
static bool first = true;
if (first) {
- unsigned long sz = 0x100;
+ unsigned long sz = 0x10;
pmu_set_power_domain(PD_A9_1, false);
- memcpy(RK30_IMEM_BASE + sz - 4, (void *)rk30_sram_secondary_startup + sz - 4, 4);
memcpy(RK30_IMEM_BASE, rk30_sram_secondary_startup, sz);
flush_icache_range((unsigned long)RK30_IMEM_BASE, (unsigned long)RK30_IMEM_BASE + sz);
outer_clean_range(0, sz);