\r
\r
/**************************************vd regulator functions***************************************/\r
+static void dvfs_volt_up_delay(struct vd_node *vd,int new_volt, int old_volt)\r
+{\r
+ int u_time;\r
+ if(new_volt<=old_volt)\r
+ return;\r
+ if(vd->volt_time_flag>0) \r
+ u_time=regulator_set_voltage_time(vd->regulator,old_volt,new_volt);\r
+ else\r
+ u_time=-1; \r
+ if(u_time<0)// regulator is not suported time,useing default time\r
+ {\r
+ DVFS_DBG("%s:vd %s is not suported getting delay time,so we use default\n",\r
+ __FUNCTION__,vd->name);\r
+ u_time=((new_volt) - (old_volt)) >> 9;\r
+ }\r
+ DVFS_DBG("%s:vd %s volt %d to %d delay %d us\n",__FUNCTION__,vd->name,\r
+ old_volt,new_volt,u_time);\r
+ if (u_time >= 1000) {\r
+ mdelay(u_time / 1000);\r
+ udelay(u_time % 1000);\r
+ DVFS_ERR("regulator set vol delay is larger 1ms,old is %d,new is %d\n",old_volt,new_volt);\r
+ } else if (u_time) {\r
+ udelay(u_time);\r
+ } \r
+}\r
int dvfs_regulator_set_voltage_readback(struct regulator *regulator, int min_uV, int max_uV)\r
{\r
int ret = 0, read_back = 0;\r
}\r
mutex_unlock(&mutex);\r
}\r
+void dvfs_vd_get_regulator_volt_time_info(struct vd_node *vd)\r
+{\r
+ if(vd->volt_time_flag<=0)// check regulator support get uping vol timer\r
+ {\r
+ vd->volt_time_flag=dvfs_regulator_set_voltage_time(vd->regulator,vd->cur_volt,vd->cur_volt+200*1000);\r
+ if(vd->volt_time_flag<0)\r
+ {\r
+ DVFS_DBG("%s,vd %s volt_time is no support\n",__FUNCTION__,vd->name);\r
+ }\r
+ else\r
+ {\r
+ DVFS_DBG("%s,vd %s volt_time is support,up 200mv need delay %d us\n",__FUNCTION__,vd->name,vd->volt_time_flag);\r
+\r
+ } \r
+ }\r
+}\r
+\r
+void dvfs_vd_get_regulator_mode_info(struct vd_node *vd)\r
+{\r
+ //REGULATOR_MODE_FAST\r
+ if(vd->mode_flag<=0)// check regulator support get uping vol timer\r
+ {\r
+ vd->mode_flag=dvfs_regulator_get_mode(vd->regulator);\r
+ if(vd->mode_flag==REGULATOR_MODE_FAST||vd->mode_flag==REGULATOR_MODE_NORMAL\r
+ ||vd->mode_flag==REGULATOR_MODE_IDLE||vd->mode_flag==REGULATOR_MODE_STANDBY)\r
+ {\r
+ if(dvfs_regulator_set_mode(vd->regulator,vd->mode_flag)<0)\r
+ {\r
+ vd->mode_flag=0;// check again\r
+ }\r
+ \r
+ }\r
+ if(vd->mode_flag>0)\r
+ {\r
+ DVFS_DBG("%s,vd %s mode(now is %d) support\n",__FUNCTION__,vd->name,vd->mode_flag);\r
+ }\r
+ else\r
+ {\r
+ DVFS_DBG("%s,vd %s mode is not support now check\n",__FUNCTION__,vd->name);\r
+\r
+ }\r
+ \r
+ }\r
+}\r
struct regulator *dvfs_get_regulator(char *regulator_name) \r
{\r
struct vd_node *vd;\r
// DVFS_DBG("dvfs_regulator_get(%s)\n",dvfs_clk->vd->regulator_name);\r
clk_enable_dvfs_regulator_check(dvfs_clk->vd);\r
dvfs_get_vd_regulator_volt_list(dvfs_clk->vd);\r
+ dvfs_vd_get_regulator_volt_time_info(dvfs_clk->vd);\r
+ //dvfs_vd_get_regulator_mode_info(dvfs_clk->vd);\r
} else {\r
//dvfs_clk->vd->regulator = NULL;\r
dvfs_clk->enable_dvfs = 0;\r
list_add(&vd->node, &rk_dvfs_tree);\r
INIT_LIST_HEAD(&vd->pd_list);\r
INIT_LIST_HEAD(&vd->req_volt_list);\r
-\r
+ vd->mode_flag=0;\r
+ vd->volt_time_flag=0;\r
+ vd->n_voltages=0;\r
mutex_unlock(&mutex);\r
return 0;\r
}\r
if (vd_clk->cur_volt != volt) {\r
DVFS_DBG("\t\t%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt);\r
ret = dvfs_regulator_set_voltage_readback(regulator, volt, volt);\r
- udelay(get_volt_up_delay(volt, volt_pre));\r
+ //udelay(get_volt_up_delay(volt, volt_pre));\r
+ dvfs_volt_up_delay(vd_clk,volt, volt_pre);\r
if (ret < 0) {\r
DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new, volt_old);\r
if (vd_dep->cur_volt != volt_dep) {\r
DVFS_DBG("\t\t%s:%d->%d\n", vd_dep->name, vd_dep->cur_volt, volt_dep);\r
ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep, volt_dep);\r
- udelay(get_volt_up_delay(volt_dep, volt_dep_pre));\r
+ //udelay(get_volt_up_delay(volt_dep, volt_dep_pre));\r
+ dvfs_volt_up_delay(vd_dep,volt_dep, volt_dep_pre);\r
if (ret < 0) {\r
DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
DVFS_DBG("ENTER %s, volt=%d(old=%d)\n", __func__, volt_new, vd_clk->cur_volt);\r
if (!IS_ERR_OR_NULL(vd_clk->regulator)) {\r
ret = dvfs_regulator_set_voltage_readback(vd_clk->regulator, volt_new, volt_new);\r
- udelay(get_volt_up_delay(volt_new, vd_clk->cur_volt));\r
+ //udelay(get_volt_up_delay(volt_new, vd_clk->cur_volt));\r
+ dvfs_volt_up_delay(vd_clk,volt_new, vd_clk->cur_volt);\r
if (ret < 0) {\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
if (vd_clk->cur_volt != volt_new_corrected) {\r
DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_new_corrected);\r
ret = dvfs_regulator_set_voltage_readback(regulator, volt_new_corrected, volt_new_corrected);\r
- udelay(get_volt_up_delay(volt_new_corrected, vd_clk->cur_volt));\r
+ //udelay(get_volt_up_delay(volt_new_corrected, vd_clk->cur_volt));\r
+ dvfs_volt_up_delay(vd_clk,volt_new_corrected, vd_clk->cur_volt);\r
if (ret < 0) {\r
DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new_corrected, vd_clk->cur_volt);\r
if (vd_dep->cur_volt != volt_dep_new_corrected) {\r
DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_dep_new_corrected);\r
ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_new_corrected, volt_dep_new_corrected);\r
- udelay(get_volt_up_delay(volt_dep_new_corrected, vd_dep->cur_volt));\r
+ //udelay(get_volt_up_delay(volt_dep_new_corrected, vd_dep->cur_volt));\r
+ dvfs_volt_up_delay(vd_dep,volt_dep_new_corrected, vd_dep->cur_volt);\r
if (ret < 0) {\r
DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_dep->name, ret, volt_dep_new_corrected, vd_dep->cur_volt);\r