rk3288: fix the bug when dclk_lcdc select gpll as parent

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 604a94f8b91673e2141df58fbe76b5e688bf4af8..d80bff0c10d8e70b9a1cb68cf4755e12fd98ab60 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -572,6 +572,7 @@ static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long
        if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
                *best_parent_p = gpll;
                best = rate;
+               *best_parent_rate = 297*MHZ;
        } else {
                *best_parent_p = cpll;
                div = RK3288_LIMIT_PLL_VIO0/rate;
@@ -630,6 +631,7 @@ static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long
        if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
                *best_parent_p = gpll;
                best = rate;
+               *best_parent_rate = 297*MHZ;
        } else {
                *best_parent_p = cpll;
                div = RK3288_LIMIT_PLL_VIO1/rate;