UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3399

There are 2 IP blocks pin routes need to be switched, that are
uart2dbg, pcie_clkreq.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit accc1ce7d2ffc6419a8eaf8c0190d9240df0c43f)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I940fbec4869f1395e66c8e693b838f58aa84a7a1

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 667dabbc5d0663235f3687f8eba86a68b1de6533..16bd40e144c5a54c29b4547861c8924ebe839f5d 100644 (file)
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -878,6 +878,45 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
        },
 };
 
+static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
+       {
+               /* uart2dbga_rx */
+               .bank_num = 4,
+               .pin = 8,
+               .func = 2,
+               .route_offset = 0xe21c,
+               .route_val = BIT(16 + 10) | BIT(16 + 11),
+       }, {
+               /* uart2dbgb_rx */
+               .bank_num = 4,
+               .pin = 16,
+               .func = 2,
+               .route_offset = 0xe21c,
+               .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
+       }, {
+               /* uart2dbgc_rx */
+               .bank_num = 4,
+               .pin = 19,
+               .func = 1,
+               .route_offset = 0xe21c,
+               .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
+       }, {
+               /* pcie_clkreqn */
+               .bank_num = 2,
+               .pin = 26,
+               .func = 2,
+               .route_offset = 0xe21c,
+               .route_val = BIT(16 + 14),
+       }, {
+               /* pcie_clkreqnb */
+               .bank_num = 4,
+               .pin = 24,
+               .func = 1,
+               .route_offset = 0xe21c,
+               .route_val = BIT(16 + 14) | BIT(14),
+       },
+};
+
 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
                                   int mux, u32 *reg, u32 *value)
 {
@@ -3571,6 +3610,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
                .pmu_mux_offset         = 0x0,
                .grf_drv_offset         = 0xe100,
                .pmu_drv_offset         = 0x80,
+               .iomux_routes           = rk3399_mux_route_data,
+               .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
                .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
                .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
 };