};
anatop: anatop@020c8000 {
- compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+ compatible = "fsl,imx6sl-anatop",
+ "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
#define ANADIG_USB1_CHRG_DETECT 0x1b0
#define ANADIG_USB2_CHRG_DETECT 0x210
#define ANADIG_DIGPROG 0x260
+#define ANADIG_DIGPROG_IMX6SL 0x280
#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
void __iomem *anatop_base;
unsigned int revision;
u32 digprog;
+ u16 offset = ANADIG_DIGPROG;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
WARN_ON(!anatop_base);
- digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG);
+ if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
+ offset = ANADIG_DIGPROG_IMX6SL;
+ digprog = readl_relaxed(anatop_base + offset);
iounmap(anatop_base);
switch (digprog & 0xff) {