For ARM load/store instructions, encode [reg+reg] with no shifter immediate as

a left shift by zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 7b0bf12bffcd06baf55f49249ce871a844a15822..bd799f233c07373141878b7e239353433f1bd9aa 100644 (file)
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -277,6 +277,9 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
   // ROR - 11
   switch (ShOp) {
   default: llvm_unreachable("Unknown shift opc!");
+  case ARM_AM::no_shift:
+    assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
+    // fall through
   case ARM_AM::lsl: SBits = 0x0; break;
   case ARM_AM::lsr: SBits = 0x1; break;
   case ARM_AM::asr: SBits = 0x2; break;