dsb();
}
+static void __init rk30_io_drive_strength_init(void)
+{
+#if defined(CONFIG_ARCH_RK3066B)
+ writel_relaxed(0x11001100, RK30_GRF_BASE + GRF_IO_CON4);
+#endif
+}
+
#define L2_LY_SP_OFF (0)
#define L2_LY_SP_MSK (0x7)
rk30_map_common_io();
rk29_setup_early_printk();
rk30_cpu_axi_init();
+ rk30_io_drive_strength_init();
rk29_sram_init();
board_clock_init();
rk30_l2_cache_init();
#define GRF_DMAC2_CON1 0x00c0
#define GRF_DMAC2_CON2 0x00c4
#define GRF_DMAC2_CON3 0x00c8
+#define GRF_IO_CON0 0x00f4
+#define GRF_IO_CON1 0x00f8
+#define GRF_IO_CON2 0x00fc
+#define GRF_IO_CON3 0x0100
+#define GRF_IO_CON4 0x0104
#define GRF_UOC0_CON0 0x010c
#define GRF_UOC0_CON1 0x0110
#define GRF_UOC0_CON2 0x0114