" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
" beqzl %0, 1b \n" \
- " addu %0, %1, %3 \n" \
+ " " #asm_op " %0, %1, %3 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), "+m" (v->counter) \
: "Ir" (i)); \
: "Ir" (i)); \
} while (unlikely(!result)); \
\
- result = temp + i; \
+ result = temp; result c_op i; \
} else { \
unsigned long flags; \
\
: "memory"); \
} while (unlikely(!result)); \
\
- result = temp + i; \
+ result = temp; result c_op i; \
} else { \
unsigned long flags; \
\