This target does not support/want ISD::BRCONDTWOWAY

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21164 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 44a8ef49b7700bf8adafcc65f06a817b3ce65702..787edb91897503f65704f04e3279a84e413e5763 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -62,6 +62,7 @@ namespace {
       addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
       addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
       
+      setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
       setOperationAction(ISD::EXTLOAD  , MVT::i1   , Promote);
       setOperationAction(ISD::EXTLOAD  , MVT::f32  , Promote);
 

diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 13a4689bd31d793ef8ef904c7a709d5baea11dd8..07c536adf1ddb85d367b2e4689fad87648bce048 100644 (file)
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -55,6 +55,7 @@ namespace {
       // register class for predicate registers 
       addRegisterClass(MVT::i1, IA64::PRRegisterClass);
       
+      setOperationAction(ISD::BRCONDTWOWAY     , MVT::Other, Expand);
       setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
 
       setSetCCResultType(MVT::i1); 

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 322d1299499b182c0a48613192e8520f2a17f41e..61b7e597e1aba7a2bd1488c821671d88095f5c5e 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -56,6 +56,7 @@ namespace {
       // well.
 /**/  addRegisterClass(MVT::i1, X86::R8RegisterClass);
 
+      setOperationAction(ISD::BRCONDTWOWAY     , MVT::Other, Expand);
       setOperationAction(ISD::MEMMOVE          , MVT::Other, Expand);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
       setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i16  , Expand);