Legalize FSQRT, FSIN, FCOS nodes, patch contributed by Morten Ofstad

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21606 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 20912583d7168e2c6df6227c1e6b11b8bd042899..b8d07d0cbf5a687b450a646716eaca7bde39612f 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -990,6 +990,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     // Unary operators
   case ISD::FABS:
   case ISD::FNEG:
+  case ISD::FSQRT:
+  case ISD::FSIN:
+  case ISD::FCOS:
     Tmp1 = LegalizeOp(Node->getOperand(0));
     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
     case TargetLowering::Legal:
@@ -1335,6 +1338,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     // precision, and these operations don't modify precision at all.
     break;
 
+  case ISD::FSQRT:
+  case ISD::FSIN:
+  case ISD::FCOS:
+    Tmp1 = PromoteOp(Node->getOperand(0));
+    assert(Tmp1.getValueType() == NVT);
+    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
+    if(NoExcessFPPrecision)
+      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
+    break;
+
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR: