The return value of this call is not used, so no point

in assigning it to a variable (gcc-4.6 warning).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 0275a505e85e5bbe86dd09769d5155e017212957..389fd19a8efc0c7392d0861456609524bb249677 100644 (file)
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -628,14 +628,13 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
     case ARM::MOVsrl_flag:
     case ARM::MOVsra_flag: {
       // These are just fancy MOVs insructions.
-      MachineInstrBuilder MIB =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
-                               MI.getOperand(0).getReg())
-        .addOperand(MI.getOperand(1))
-        .addReg(0)
-        .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
-                                     : ARM_AM::asr), 1)))
-        .addReg(ARM::CPSR, RegState::Define);
+      AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
+                             MI.getOperand(0).getReg())
+      .addOperand(MI.getOperand(1))
+      .addReg(0)
+      .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
+                                   : ARM_AM::asr), 1)))
+      .addReg(ARM::CPSR, RegState::Define);
       MI.eraseFromParent();
       break;
     }