return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
+static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
+ assert(0 && "Not implemented");
+}
+
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default:
assert(0 && "Should not custom lower this!");
abort();
+ case ISD::FORMAL_ARGUMENTS:
+ return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::RET:
return LowerRET(Op, DAG);
}
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
+def BX: InstARM<(ops), "bx", [(retflag)]>;
+
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldr $dst, [$addr]",
[(set IntRegs:$dst, (load IntRegs:$addr))]>;
"str $src, [$addr]",
[(store IntRegs:$src, IntRegs:$addr)]>;
-def mov : InstARM<(ops IntRegs:$dst, IntRegs:$b),
- "mov $dst, $b", []>;
+def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
+ "mov $dst, $src", []>;
+
+def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
+ "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,