#define CHANNEL_2_EN (1<<15)
#define CHANNEL_3_EN (2<<15)
#define CHANNLE_4_EN (3<<15)
-#ifdef CONFIG_ARCH_RK29
#define TX_MODE_MASTER (0<<13)
#define TX_MODE_SLAVE (1<<13)
-#else
-#define TX_MODE_MASTER (0<<27)
-#define TX_MODE_SLAVE (1<<27)
-#endif
-
#define RESET_TX (1<<17)
#define RESET_RX (1<<16)
#define I2S_DMA_REQ1_DISABLE (1<<6)
#define I2S_HWT_16BIT (0<<14)
#define I2S_HWT_32BIT (1<<14)
+
#ifdef CONFIG_ARCH_RK29
-#define I2S_MASTER_MODE (0<<13)
-#define I2S_SLAVE_MODE (1<<13)
-#define I2S_MODE_MASK (1<<13)
-#else
-#define I2S_MASTER_MODE (0<<27)
-#define I2S_SLAVE_MODE (1<<27)
-#define I2S_MODE_MASK (1<<27)
+ #define I2S_MASTER_MODE (0<<13)
+ #define I2S_SLAVE_MODE (1<<13)
+ #define I2S_MODE_MASK (1<<13)
#endif
+
#define I2S_JUSTIFIED_RIGHT (0<<12)
#define I2S_JUSTIFIED_LEFT (1<<12)
/* I2S_TXCKR */
-#define I2S_TSP_POSEDGE (0<<25)
-#define I2S_TSP_NEGEDGE (1<<25)
-#define I2S_TLP_NORMAL (0<<24)
-#define I2S_TLP_OPPSITE (1<<24)
-
-#define I2S_MCLK_DIV(x) ((0xFF&x)<<16)
-#define I2S_MCLK_DIV_MASK ((0xFF)<<16)
+#ifdef CONFIG_ARCH_RK29
+ #define I2S_TSP_POSEDGE (0<<25)
+ #define I2S_TSP_NEGEDGE (1<<25)
+ #define I2S_TLP_NORMAL (0<<24)
+ #define I2S_TLP_OPPSITE (1<<24)
-#define I2S_TSD_FIXED (0<<12)
-#define I2S_TSD_CHANGED (1<<12)
+ #define I2S_MCLK_DIV(x) ((0xFF&x)<<16)
+ #define I2S_MCLK_DIV_MASK ((0xFF)<<16)
-#define I2S_TX_LRCK_NO_DELAY (0<<10)
-#define I2S_TX_LRCK_DELAY_ONE (1<<10)
-#define I2S_TX_LRCK_DELAY_TWO (2<<10)
-#define I2S_TX_LRCK_DELAY_THREE (3<<10)
-#define I2S_TX_LRCK_DELAY_MASK (3<<10)
+ #define I2S_TSD_FIXED (0<<12)
+ #define I2S_TSD_CHANGED (1<<12)
-#define I2S_TX_SCLK_DIV(x) (x&0x3FF)
-#define I2S_TX_SCLK_DIV_MASK (0x3FF);
+ #define I2S_TX_LRCK_NO_DELAY (0<<10)
+ #define I2S_TX_LRCK_DELAY_ONE (1<<10)
+ #define I2S_TX_LRCK_DELAY_TWO (2<<10)
+ #define I2S_TX_LRCK_DELAY_THREE (3<<10)
+ #define I2S_TX_LRCK_DELAY_MASK (3<<10)
+ #define I2S_TX_SCLK_DIV(x) (x&0x3FF)
+ #define I2S_TX_SCLK_DIV_MASK (0x3FF);
+#else
+//I2S_CKR
+ #define I2S_MASTER_MODE (0<<27)
+ #define I2S_SLAVE_MODE (1<<27)
+ #define I2S_MODE_MASK (1<<27)
+
+ #define I2S_BCLK_POSEDGE (0<<26)//sclk polarity invert??
+ #define I2S_BCLK_NEGEDGE (1<<26)
+
+ #define I2S_RX_LRCK_POSEDGE (0<<25)//LRCK polarity invert??
+ #define I2S_RX_LRCK_NEGEDGE (1<<25)
+
+ #define I2S_TX_LRCK_POSEDGE (0<<24)
+ #define I2S_TX_LRCK_NEGEDGE (1<<24)
+
+ #define I2S_MCLK_DIV(x) ((0xFF&x)<<16)
+ #define I2S_MCLK_DIV_MASK ((0xFF)<<16)
+
+ #define I2S_TX_SCLK_DIV(x) (x&0xFF)
+ #define I2S_TX_SCLK_DIV_MASK (0xFF);
+#endif
/* I2S_DMACR */
#define I2S_RECE_DMA_DISABLE (0<<24)
#define I2S_TX_TRAN_STOP (0<<0)
#define I2S_TX_TRAN_START (1<<0)
-
+#ifdef CONFIG_ARCH_RK29
#define I2S_TXR_BUFF 0x20
#define I2S_RXR_BUFF 0x24
-
-#ifdef CONFIG_ARCH_RK29
//I2S Registers
typedef volatile struct tagIIS_STRUCT
{
unsigned int I2S_RXRST;
}I2S_REG,*pI2S_REG;
#else
+#define I2S_TXR_BUFF 0x24
+#define I2S_RXR_BUFF 0x28
typedef volatile struct tagIIS_STRUCT
{
unsigned int I2S_TXCR;//0xF 0
}
I2S_DBG("Enter::%s----%d, I2S_TXCR=0x%X\n",__FUNCTION__,__LINE__,tx_ctl);
#if 0//defined(CONFIG_SND_RK29_SOC_alc5631) || defined(CONFIG_SND_RK29_SOC_alc5621)
- rx_ctl = tx_ctl;
- rx_ctl &= ~I2S_MODE_MASK;
- rx_ctl |= I2S_SLAVE_MODE; // set tx slave, rx master
- writel(rx_ctl, &(pheadi2s->I2S_TXCR));
+ rx_ctl = tx_ctl;
+ rx_ctl &= ~I2S_MODE_MASK;
+ rx_ctl |= I2S_SLAVE_MODE; // set tx slave, rx master
+ writel(rx_ctl, &(pheadi2s->I2S_TXCR));
#else
- writel(tx_ctl, &(pheadi2s->I2S_TXCR));
+ writel(tx_ctl, &(pheadi2s->I2S_TXCR));
#endif
rx_ctl = tx_ctl & 0x00007FFF;
writel(rx_ctl, &(pheadi2s->I2S_RXCR));
iismod |= I2S_DATA_WIDTH(31);
break;
}
+
iis_ckr_value = readl(&(pheadi2s->I2S_CKR));
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
iis_ckr_value &= ~I2S_SLAVE_MODE;
iis_ckr_value |= I2S_SLAVE_MODE;
#endif
writel(iis_ckr_value, &(pheadi2s->I2S_CKR));
+
// writel((16<<24) |(16<<18)|(16<<12)|(16<<6)|16, &(pheadi2s->I2S_FIFOLR));
dmarc = readl(&(pheadi2s->I2S_DMACR));
writel(dmarc, &(pheadi2s->I2S_DMACR));
I2S_DBG("Enter %s, %d I2S_TXCR=0x%08X\n", __func__, __LINE__, iismod);
#if 0//defined(CONFIG_SND_RK29_SOC_alc5631) || defined(CONFIG_SND_RK29_SOC_alc5621)
- dmarc = iismod;
- dmarc &= ~I2S_MODE_MASK;
- dmarc |= I2S_SLAVE_MODE; // set tx slave, rx master
- writel(dmarc, &(pheadi2s->I2S_TXCR));
+ dmarc = iismod;
+ dmarc &= ~I2S_MODE_MASK;
+ dmarc |= I2S_SLAVE_MODE; // set tx slave, rx master
+ writel(dmarc, &(pheadi2s->I2S_TXCR));
#else
- writel(iismod, &(pheadi2s->I2S_TXCR));
+ writel(iismod, &(pheadi2s->I2S_TXCR));
#endif
iismod = iismod & 0x00007FFF;
writel(iismod, &(pheadi2s->I2S_RXCR));
+
return 0;
}
return ret;
}
+
/*
- * Set Rockchip Clock source
+ * Set Rockchip I2S MCLK source
*/
static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
i2s = to_info(cpu_dai);
I2S_DBG("Enter:%s, %d, i2s=0x%p, freq=%d\n", __FUNCTION__, __LINE__, i2s, freq);
- /*add scu clk source and enable clk*/
- clk_set_rate(i2s->iis_clk, freq);
+ /*add scu clk source and enable clk*/
+// clk_set_rate(i2s->iis_clk, freq);
return 0;
}
static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
int div_id, int div)
{
-/*
struct rk29_i2s_info *i2s;
- u32 reg;
+ u32 reg;
i2s = to_info(cpu_dai);
//stereo mode MCLK/SCK=4
- reg = readl(&(pheadi2s->I2S_TXCKR));
+ reg = readl(&(pheadi2s->I2S_CKR));
I2S_DBG("Enter:%s, %d, div_id=0x%08X, div=0x%08X\n", __FUNCTION__, __LINE__, div_id, div);
//when i2s in master mode ,must set codec pll div
switch (div_id) {
case ROCKCHIP_DIV_BCLK:
- reg &= ~I2S_TX_SCLK_DIV_MASK;
- reg |= I2S_TX_SCLK_DIV(div);
- break;
+ reg &= ~I2S_TX_SCLK_DIV_MASK;
+ reg |= I2S_TX_SCLK_DIV(div);
+ break;
case ROCKCHIP_DIV_MCLK:
- reg &= ~I2S_MCLK_DIV_MASK;
- reg |= I2S_MCLK_DIV(div);
- break;
+ reg &= ~I2S_MCLK_DIV_MASK;
+ reg |= I2S_MCLK_DIV(div);
+ break;
case ROCKCHIP_DIV_PRESCALER:
-
- break;
+ break;
default:
- return -EINVAL;
+ return -EINVAL;
}
- writel(reg, &(pheadi2s->I2S_TXCKR));
- writel(reg, &(pheadi2s->I2S_RXCKR));
-*/
+ writel(reg, &(pheadi2s->I2S_CKR));
+
return 0;
}
rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D_I2S2_2CH_SDO);
break;
default:
- I2S_DBG("Enter:%s, %d, Error For DevId!!!", __FUNCTION__, __LINE__);
- return -EINVAL;
+ I2S_DBG("Enter:%s, %d, Error For DevId!!!", __FUNCTION__, __LINE__);
+ return -EINVAL;
}
- return 0;
+ return 0;
}
static int rk29_i2s_probe(struct platform_device *pdev,
dev_err(dev, "cannot ioremap registers\n");
return -ENXIO;
}
-
+#if 0
i2s->iis_pclk = clk_get(dev, "i2s");
if (IS_ERR(i2s->iis_pclk)) {
dev_err(dev, "failed to get iis_clock\n");
}
clk_enable(i2s->iis_pclk);
-
+#endif
/* Mark ourselves as in TXRX mode so we can run through our cleanup
* process without warnings. */
rockchip_snd_txctrl(i2s, 0, true);
WARN_ON(rk29_dma_request(i2s->dma_playback->channel, i2s->dma_playback->client, NULL));
WARN_ON(rk29_dma_request(i2s->dma_capture->channel, i2s->dma_capture->client, NULL));
#endif
+#if 0
i2s->iis_clk = clk_get(&pdev->dev, "i2s");
I2S_DBG("Enter:%s, %d, iis_clk=%p\n", __FUNCTION__, __LINE__, i2s->iis_clk);
if (IS_ERR(i2s->iis_clk)) {
clk_enable(i2s->iis_clk);
clk_set_rate(i2s->iis_clk, 11289600);
+#endif
ret = rk29_i2s_probe(pdev, dai, i2s, 0);
if (ret)
goto err_clk;
ret = snd_soc_register_dai(&pdev->dev, dai);
if (ret != 0)
goto err_i2sv2;
+#if 0
+ writel(0x0000000F, &(pheadi2s->I2S_TXCR));
+ writel(0x0000000F, &(pheadi2s->I2S_RXCR));
+ writel(0x00071f1F, &(pheadi2s->I2S_CKR));
+ writel(0x001F0110, &(pheadi2s->I2S_DMACR));
+ writel(0x00000003, &(pheadi2s->I2S_XFER));
+ while(1)
+ {
+ writel(0x5555aaaa, &(pheadi2s->I2S_TXDR));
+ // msleep(1);
+ // printk("-----------------------\n");
+ }
+#endif
+
+
return 0;
#include <linux/seq_file.h>
static int proc_i2s_show(struct seq_file *s, void *v)
{
+#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
+ struct rk29_i2s_info *i2s=&rk29_i2s[0];
+#elif CONFIG_SND_RK29_SOC_I2S_2CH
struct rk29_i2s_info *i2s=&rk29_i2s[1];
+#else
+ struct rk29_i2s_info *i2s=&rk29_i2s[2];
+#endif
printk("========Show I2S reg========\n");
printk("I2S_TXCR = 0x%08X\n", readl(&(pheadi2s->I2S_TXCR)));
projects / firefly-linux-kernel-4.4.55.git / commitdiff