Fixed bug when generating Load Upper Immediate microMIPS instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index f0d82dc335b234ab6d03313a20fbe3fbfc19ca53..68872fe8f2ffc2d5b5384d4e244c1f458ae370ed 100644 (file)
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -363,7 +363,7 @@ class CLO_FM<bits<6> funct> : StdArch {
   let rt = rd;
 }
 
-class LUI_FM {
+class LUI_FM : StdArch {
   bits<5> rt;
   bits<16> imm16;
 

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 1c6b3cd90639677f754a64acce2fd49ba68f1c3d..4795969175af1b3f184c4cf5338e1b9e499e1e9d 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -447,7 +447,7 @@ class shift_rotate_reg<string opstr, RegisterOperand RO,
 // Load Upper Imediate
 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
   InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
-         [], IIArith, FrmI>, IsAsCheapAsAMove {
+         [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
   let neverHasSideEffects = 1;
   let isReMaterializable = 1;
 }

diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt
index a6a3575a5aa0cf281529d104502032776c9e1d57..30e2b5719c91ed83a182c9993cd5820e54689bad 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips.txt
+++ b/test/MC/Disassembler/Mips/micromips.txt
@@ -49,6 +49,9 @@
 # CHECK: sltu $3, $3, $5
 0x00 0xa3 0x1b 0x90
 
+# CHECK: lui $9, 17767
+0x41 0xa9 0x45 0x67
+
 # CHECK: and $9, $6, $7
 0x00 0xe6 0x4a 0x50
 

diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt
index 253223cc458dde046fa22387b5c7b27d76b234db..ff77de518774aae7dee36aa93906d38db7ebdd93 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips_le.txt
+++ b/test/MC/Disassembler/Mips/micromips_le.txt
@@ -49,6 +49,9 @@
 # CHECK: sltu $3, $3, $5
 0xa3 0x00 0x90 0x1b
 
+# CHECK: lui $9, 17767
+0xa9 0x41 0x67 0x45
+
 # CHECK: and $9, $6, $7
 0xe6 0x00 0x50 0x4a
 

diff --git a/test/MC/Mips/micromips-alu-instructions.s b/test/MC/Mips/micromips-alu-instructions.s
index bd5cdd3ba86233827f3ca6329d2c458717b9b355..276a83e82c03ec32231388d8c7a51a7eab13f3d3 100644 (file)
--- a/test/MC/Mips/micromips-alu-instructions.s
+++ b/test/MC/Mips/micromips-alu-instructions.s
@@ -23,6 +23,7 @@
 # CHECK-EL: slti   $3, $3, 103    # encoding: [0x63,0x90,0x67,0x00]
 # CHECK-EL: sltiu  $3, $3, 103    # encoding: [0x63,0xb0,0x67,0x00]
 # CHECK-EL: sltu   $3, $3, $5     # encoding: [0xa3,0x00,0x90,0x1b]
+# CHECK-EL: lui    $9, 17767      # encoding: [0xa9,0x41,0x67,0x45]
 # CHECK-EL: and    $9, $6, $7     # encoding: [0xe6,0x00,0x50,0x4a]
 # CHECK-EL: andi   $9, $6, 17767  # encoding: [0x26,0xd1,0x67,0x45]
 # CHECK-EL: andi   $9, $6, 17767  # encoding: [0x26,0xd1,0x67,0x45]
@@ -57,6 +58,7 @@
 # CHECK-EB: slti  $3, $3, 103     # encoding: [0x90,0x63,0x00,0x67]
 # CHECK-EB: sltiu $3, $3, 103     # encoding: [0xb0,0x63,0x00,0x67]
 # CHECK-EB: sltu  $3, $3, $5      # encoding: [0x00,0xa3,0x1b,0x90]
+# CHECK-EB: lui $9, 17767         # encoding: [0x41,0xa9,0x45,0x67]
 # CHECK-EB: and $9, $6, $7        # encoding: [0x00,0xe6,0x4a,0x50]
 # CHECK-EB:  andi  $9, $6, 17767  # encoding: [0xd1,0x26,0x45,0x67]
 # CHECK-EB:  andi  $9, $6, 17767  # encoding: [0xd1,0x26,0x45,0x67]
@@ -88,6 +90,7 @@
     slti   $3, $3, 103
     sltiu  $3, $3, 103
     sltu   $3, $3, $5
+    lui    $9, 17767
     and    $9, $6, $7
     and    $9, $6, 17767
     andi   $9, $6, 17767