add a mayLoad property for machine instructions, a correlary to mayStore.

This is currently not set by anything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h
index 8879246115157f55ef6135476f44420a26aa611b..ded965876e92d7682f4fb509ea1779a9313fcd93 100644 (file)
--- a/include/llvm/Target/TargetInstrDesc.h
+++ b/include/llvm/Target/TargetInstrDesc.h
@@ -90,6 +90,7 @@ namespace TID {
     NotDuplicable,
     DelaySlot,
     SimpleLoad,
+    MayLoad,
     MayStore,
     NeverHasSideEffects,
     MayHaveSideEffects,
@@ -308,6 +309,14 @@ public:
   //===--------------------------------------------------------------------===//
   // Side Effect Analysis
   //===--------------------------------------------------------------------===//
+
+  /// mayLoad - Return true if this instruction could possibly read memory.
+  /// Instructions with this flag set are not necessarily simple load
+  /// instructions, they may load a value and modify it, for example.
+  bool mayLoad() const {
+    return Flags & (1 << TID::MayLoad);
+  }
+  
   
   /// mayStore - Return true if this instruction could possibly modify memory.
   /// Instructions with this flag set are not necessarily simple store
@@ -317,8 +326,6 @@ public:
     return Flags & (1 << TID::MayStore);
   }
   
-  // TODO: mayLoad.
-  
   /// hasNoSideEffects - Return true if all instances of this instruction are
   /// guaranteed to have no side effects other than:
   ///   1. The register operands that are def/used by the MachineInstr.

diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index daab0654a410f88624be536d98299575eac3b585..9778db3ccfd3e06d95f27851a82ad656298671dc 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -84,6 +84,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   isSimpleLoad = R->getValueAsBit("isSimpleLoad");
+  mayLoad      = R->getValueAsBit("mayLoad");
   mayStore     = R->getValueAsBit("mayStore");
   isImplicitDef= R->getValueAsBit("isImplicitDef");
   bool isTwoAddress = R->getValueAsBit("isTwoAddress");

diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 6f7a19efffae69fc301b32eb2f579e6225655cab..f3cdbfec9f9171e05e9e795aab98c550b1b3ba78 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -90,7 +90,7 @@ namespace llvm {
     bool isBarrier;
     bool isCall;
     bool isSimpleLoad;
-    bool mayStore;
+    bool mayLoad, mayStore;
     bool isImplicitDef;
     bool isPredicable;
     bool isConvertibleToThreeAddress;

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index d357f33f1a897913d7bdb4f773b97ea5dcd6424a..1c1973f9a50f87b491b16f188888e0bf2ca31e87 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -144,12 +144,12 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
 class InstAnalyzer {
   const CodeGenDAGPatterns &CDP;
   bool &mayStore;
-  bool &isLoad;
+  bool &mayLoad;
   bool &NeverHasSideEffects;
 public:
   InstAnalyzer(const CodeGenDAGPatterns &cdp,
-               bool &maystore, bool &isload, bool &nhse)
-    : CDP(cdp), mayStore(maystore), isLoad(isload), NeverHasSideEffects(nhse) {
+               bool &maystore, bool &mayload, bool &nhse)
+    : CDP(cdp), mayStore(maystore), mayLoad(mayload), NeverHasSideEffects(nhse){
   }
   
   void Analyze(Record *InstRecord) {
@@ -166,9 +166,8 @@ public:
   
 private:
   void AnalyzeNode(const TreePatternNode *N) {
-    if (N->isLeaf()) {
+    if (N->isLeaf())
       return;
-    }
 
     if (N->getOperator()->getName() != "set") {
       // Get information about the SDNode for the operator.
@@ -191,11 +190,11 @@ private:
 };
 
 void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, 
-                                        bool &mayStore, bool &isLoad, 
+                                        bool &mayStore, bool &mayLoad, 
                                         bool &NeverHasSideEffects) {
-  mayStore = isLoad = NeverHasSideEffects = false;
+  mayStore = mayLoad = NeverHasSideEffects = false;
   
-  InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
+  InstAnalyzer(CDP, mayStore, mayLoad,NeverHasSideEffects).Analyze(Inst.TheDef);
 
   // InstAnalyzer only correctly analyzes mayStore so far.
   if (Inst.mayStore) {  // If the .td file explicitly sets mayStore, use it.
@@ -210,7 +209,7 @@ void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
   }
 
   // These two override everything.
-  isLoad              = Inst.isSimpleLoad;
+  mayLoad             = Inst.mayLoad;
   NeverHasSideEffects = Inst.neverHasSideEffects;
 
 #if 0
@@ -281,8 +280,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   const OperandInfoMapTy &OpInfo,
                                   std::ostream &OS) {
   // Determine properties of the instruction from its pattern.
-  bool mayStore, isSimpleLoad, NeverHasSideEffects;
-  InferFromPattern(Inst, mayStore, isSimpleLoad, NeverHasSideEffects);
+  bool mayStore, mayLoad, NeverHasSideEffects;
+  InferFromPattern(Inst, mayStore, mayLoad, NeverHasSideEffects);
   
   if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
     std::cerr << "error: Instruction '" << Inst.TheDef->getName()
@@ -308,7 +307,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isBarrier)    OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)       OS << "|(1<<TID::Call)";
-  if (isSimpleLoad)      OS << "|(1<<TID::SimpleLoad)";
+  if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
+  if (mayLoad)           OS << "|(1<<TID::MayLoad)";
   if (mayStore)          OS << "|(1<<TID::MayStore)";
   if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
   if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";