ARM: dts: rockchip: convert rk3288 device tree files to 64 bits

In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.

Most of the changes by the following commands:
sed -e 's/0xff/0x0 0xff/g' -e 's/0x0 0xff[[:xdigit:]]\{6\}/& 0x0/g'
sed 's/reg = <0x0 0x80000000>/reg = <0x0 0x0 0x0 0x80000000>/'
sed 's/reg = <0 0x80000000>/reg = <0x0 0x0 0x0 0x80000000>/'
sed 's/reg = <0 0x8000000>/reg = <0x0 0x0 0x0 0x8000000>/'

Change-Id: Ic4711ae04abc03db9ee09f78223a955a66a85d60
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3288-android.dtsi b/arch/arm/boot/dts/rk3288-android.dtsi
index 4f44e83b267b10d6e04893baaf0b318cda1344a1..9fddfe72bc2b0e9b47c77078bf7bc90eb5d758eb 100644 (file)
--- a/arch/arm/boot/dts/rk3288-android.dtsi
+++ b/arch/arm/boot/dts/rk3288-android.dtsi
@@ -49,12 +49,12 @@
 
        reserved-memory {
                ramoops_mem: ramoops@00000000 {
-                       reg = <0x8000000 0xF0000>;
+                       reg = <0x0 0x8000000 0x0 0xF0000>;
                };
 
                drm_logo: drm-logo@00000000 {
                compatible = "rockchip,drm-logo";
-                       reg = <0x0 0x0>;
+                       reg = <0x0 0x0 0x0 0x0>;
                };
        };
 
@@ -209,11 +209,11 @@
        dwc_control_usb: dwc-control-usb@ff770284 {
                compatible = "rockchip,rk3288-dwc-control-usb";
                status = "okay";
-               reg = <0xff770284 0x04>, <0xff770288 0x04>,
-                     <0xff7702cc 0x04>, <0xff7702d4 0x04>,
-                     <0xff770320 0x14>, <0xff770334 0x14>,
-                     <0xff770348 0x10>, <0xff770358 0x08>,
-                     <0xff770360 0x08>;
+               reg = <0x0 0xff770284 0x0 0x04>, <0x0 0xff770288 0x0 0x04>,
+                     <0x0 0xff7702cc 0x0 0x04>, <0x0 0xff7702d4 0x0 0x04>,
+                     <0x0 0xff770320 0x0 0x14>, <0x0 0xff770334 0x0 0x14>,
+                     <0x0 0xff770348 0x0 0x10>, <0x0 0xff770358 0x0 0x08>,
+                     <0x0 0xff770360 0x0 0x08>;
                reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
                            "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
                            "GRF_UOC0_BASE", "GRF_UOC1_BASE",
@@ -281,7 +281,7 @@
 
 &dmac_bus_s {
        /* change to non-secure dmac */
-       reg = <0xff600000 0x4000>;
+       reg = <0x0 0xff600000 0x0 0x4000>;
 };
 
 &efuse {

diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
index 6ff2a957387015ea8959a2f0ed59ea196e7b53a1..51bcdb8b37fdf94be71e8df1f571cfa0a68a760c 100644 (file)
--- a/arch/arm/boot/dts/rk3288-fennec.dts
+++ b/arch/arm/boot/dts/rk3288-fennec.dts
@@ -48,7 +48,7 @@
        compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
 
        memory {
-               reg = <0x0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
                device_type = "memory";
        };
 

diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 8c8692905d9bc0f606e0634b86c055d9b0645cf1..30d262a8d78a54e859a7655740d0d65e5d9603bd 100644 (file)
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -45,7 +45,7 @@
 / {
        memory {
                device_type = "memory";
-               reg = <0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
        };
 
        backlight: backlight {

diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
index eee3820747d68bcb1fbf3a33e97b16d8f42bc33e..6d3eb0a0b05b43175670c4b6ab8cba5b2ecd8f83 100644 (file)
--- a/arch/arm/boot/dts/rk3288-miniarm.dts
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -46,7 +46,7 @@
 
        memory {
                device_type = "memory";
-               reg = <0x0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
        };
 
        ext_gmac: external-gmac-clock {

diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index b67d874893ad271a2dfd1dc45ed51d5dfee8b6a8..b90b0e5969ec925583f70f9285fbdcdea7010689 100644 (file)
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -49,7 +49,7 @@
 
        memory {
                device_type = "memory";
-               reg = <0x0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
        };
 
        sound {

diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index ab7c0c095270c32a547c39acd5cc584d28307530..9abfcad395b3f3e004deb655c9d251aacf09a7d9 100644 (file)
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -55,7 +55,7 @@
         */
        memory {
                device_type = "memory";
-               reg = <0 0x8000000>;
+               reg = <0x0 0x0 0x0 0x8000000>;
        };
 
        aliases {

diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 6089a827238828f313e41818bb0361547ad3cfe7..7a498177e8fb4028a72ee663c10e4b7b4301d541 100644 (file)
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -50,7 +50,7 @@
 
        memory{
                device_type = "memory";
-               reg = <0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
        };
 
        ext_gmac: external-gmac-clock {

diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 14b9fc73c8a47f704d0b78a64a1fc42762e1d031..312f5ef403f450490818bdbda33f9de11bdcbc91 100644 (file)
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -49,7 +49,7 @@
 
        memory {
                device_type = "memory";
-               reg = <0x0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
        };
 
        ext_gmac: external-gmac-clock {

diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index bb1f01e037ba7e2a5ae8126ccff5d98b16f4a0a0..6cd794145b35d9284bc7aa96654545a2762e7118 100644 (file)
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -43,7 +43,7 @@
 
 / {
        memory {
-               reg = <0x0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
                device_type = "memory";
        };
 

diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index a48dffd2c54032ced7d67c822cec6c462d6b4449..184d73dac503d497052fc09992d58c0416f4e713 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -49,7 +49,7 @@
 / {
        memory {
                device_type = "memory";
-               reg = <0x0 0x80000000>;
+               reg = <0x0 0x0 0x0 0x80000000>;
        };
 
        gpio_keys: gpio-keys {

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2751f3fe6b23e633ae41483be95f40c91a29b337..8b920ac4bd7535f39695f92f65424fd29961f221 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -48,7 +48,7 @@
 #include <dt-bindings/soc/rockchip,boot-mode.h>
 #include <dt-bindings/suspend/rockchip-rk3288.h>
 #include <dt-bindings/display/drm_mipi_dsi.h>
-#include "skeleton.dtsi"
+#include "skeleton64.dtsi"
 
 / {
        compatible = "rockchip,rk3288";
@@ -189,13 +189,13 @@
 
        amba {
                compatible = "arm,amba-bus";
-               #address-cells = <1>;
-               #size-cells = <1>;
+               #address-cells = <2>;
+               #size-cells = <2>;
                ranges;
 
                dmac_peri: dma-controller@ff250000 {
                        compatible = "arm,pl330", "arm,primecell";
-                       reg = <0xff250000 0x4000>;
+                       reg = <0x0 0xff250000 0x0 0x4000>;
                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
@@ -207,7 +207,7 @@
 
                dmac_bus_ns: dma-controller@ff600000 {
                        compatible = "arm,pl330", "arm,primecell";
-                       reg = <0xff600000 0x4000>;
+                       reg = <0x0 0xff600000 0x0 0x4000>;
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
@@ -220,7 +220,7 @@
 
                dmac_bus_s: dma-controller@ffb20000 {
                        compatible = "arm,pl330", "arm,primecell";
-                       reg = <0xffb20000 0x4000>;
+                       reg = <0x0 0xffb20000 0x0 0x4000>;
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
@@ -232,8 +232,8 @@
        };
 
        reserved-memory {
-               #address-cells = <1>;
-               #size-cells = <1>;
+               #address-cells = <2>;
+               #size-cells = <2>;
                ranges;
 
                /*
@@ -247,7 +247,7 @@
                 * is found.
                 */
                dma-unusable@fe000000 {
-                       reg = <0xfe000000 0x1000000>;
+                       reg = <0x0 0xfe000000 0x0 0x1000000>;
                };
        };
 
@@ -270,7 +270,7 @@
 
        timer: timer@ff810000 {
                compatible = "rockchip,rk3288-timer";
-               reg = <0xff810000 0x20>;
+               reg = <0x0 0xff810000 0x0 0x20>;
                interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&xin24m>, <&cru PCLK_TIMER>;
                clock-names = "timer", "pclk";
@@ -289,7 +289,7 @@
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                fifo-depth = <0x100>;
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-               reg = <0xff0c0000 0x4000>;
+               reg = <0x0 0xff0c0000 0x0 0x4000>;
                status = "disabled";
        };
 
@@ -301,7 +301,7 @@
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                fifo-depth = <0x100>;
                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-               reg = <0xff0d0000 0x4000>;
+               reg = <0x0 0xff0d0000 0x0 0x4000>;
                status = "disabled";
        };
 
@@ -313,7 +313,7 @@
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                fifo-depth = <0x100>;
                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-               reg = <0xff0e0000 0x4000>;
+               reg = <0x0 0xff0e0000 0x0 0x4000>;
                status = "disabled";
        };
 
@@ -325,14 +325,14 @@
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                fifo-depth = <0x100>;
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-               reg = <0xff0f0000 0x4000>;
+               reg = <0x0 0xff0f0000 0x0 0x4000>;
                status = "disabled";
                supports-emmc;
        };
 
        saradc: saradc@ff100000 {
                compatible = "rockchip,saradc";
-               reg = <0xff100000 0x100>;
+               reg = <0x0 0xff100000 0x0 0x100>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                #io-channel-cells = <1>;
                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
@@ -351,7 +351,7 @@
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
-               reg = <0xff110000 0x1000>;
+               reg = <0x0 0xff110000 0x0 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
@@ -366,7 +366,7 @@
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
-               reg = <0xff120000 0x1000>;
+               reg = <0x0 0xff120000 0x0 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
@@ -381,7 +381,7 @@
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
-               reg = <0xff130000 0x1000>;
+               reg = <0x0 0xff130000 0x0 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
@@ -389,7 +389,7 @@
 
        i2c0: i2c@ff650000 {
                compatible = "rockchip,rk3288-i2c";
-               reg = <0xff650000 0x1000>;
+               reg = <0x0 0xff650000 0x0 0x1000>;
                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -402,7 +402,7 @@
 
        i2c1: i2c@ff140000 {
                compatible = "rockchip,rk3288-i2c";
-               reg = <0xff140000 0x1000>;
+               reg = <0x0 0xff140000 0x0 0x1000>;
                interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -415,7 +415,7 @@
 
        i2c3: i2c@ff150000 {
                compatible = "rockchip,rk3288-i2c";
-               reg = <0xff150000 0x1000>;
+               reg = <0x0 0xff150000 0x0 0x1000>;
                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -428,7 +428,7 @@
 
        i2c4: i2c@ff160000 {
                compatible = "rockchip,rk3288-i2c";
-               reg = <0xff160000 0x1000>;
+               reg = <0x0 0xff160000 0x0 0x1000>;
                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -441,7 +441,7 @@
 
        i2c5: i2c@ff170000 {
                compatible = "rockchip,rk3288-i2c";
-               reg = <0xff170000 0x1000>;
+               reg = <0x0 0xff170000 0x0 0x1000>;
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -454,7 +454,7 @@
 
        uart0: serial@ff180000 {
                compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
-               reg = <0xff180000 0x100>;
+               reg = <0x0 0xff180000 0x0 0x100>;
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -467,7 +467,7 @@
 
        uart1: serial@ff190000 {
                compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
-               reg = <0xff190000 0x100>;
+               reg = <0x0 0xff190000 0x0 0x100>;
                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -480,7 +480,7 @@
 
        uart2: serial@ff690000 {
                compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
-               reg = <0xff690000 0x100>;
+               reg = <0x0 0xff690000 0x0 0x100>;
                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -493,7 +493,7 @@
 
        uart3: serial@ff1b0000 {
                compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
-               reg = <0xff1b0000 0x100>;
+               reg = <0x0 0xff1b0000 0x0 0x100>;
                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -506,7 +506,7 @@
 
        uart4: serial@ff1c0000 {
                compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
-               reg = <0xff1c0000 0x100>;
+               reg = <0x0 0xff1c0000 0x0 0x100>;
                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -567,7 +567,7 @@
 
        tsadc: tsadc@ff280000 {
                compatible = "rockchip,rk3288-tsadc";
-               reg = <0xff280000 0x100>;
+               reg = <0x0 0xff280000 0x0 0x100>;
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
                clock-names = "tsadc", "apb_pclk";
@@ -586,7 +586,7 @@
 
        gmac: ethernet@ff290000 {
                compatible = "rockchip,rk3288-gmac";
-               reg = <0xff290000 0x10000>;
+               reg = <0x0 0xff290000 0x0 0x10000>;
                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "macirq", "eth_wake_irq";
@@ -606,7 +606,7 @@
 
        usb_host0_ehci: usb@ff500000 {
                compatible = "generic-ehci";
-               reg = <0xff500000 0x100>;
+               reg = <0x0 0xff500000 0x0 0x100>;
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_USBHOST0>;
                clock-names = "usbhost";
@@ -620,7 +620,7 @@
        usb_host1: usb@ff540000 {
                compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
                                "snps,dwc2";
-               reg = <0xff540000 0x40000>;
+               reg = <0x0 0xff540000 0x0 0x40000>;
                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_USBHOST1>;
                clock-names = "otg";
@@ -633,7 +633,7 @@
        usb_otg: usb@ff580000 {
                compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
                                "snps,dwc2";
-               reg = <0xff580000 0x40000>;
+               reg = <0x0 0xff580000 0x0 0x40000>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_OTG0>;
                clock-names = "otg";
@@ -649,7 +649,7 @@
 
        usb_hsic: usb@ff5c0000 {
                compatible = "generic-ehci";
-               reg = <0xff5c0000 0x100>;
+               reg = <0x0 0xff5c0000 0x0 0x100>;
                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HSIC>;
                clock-names = "usbhost";
@@ -663,10 +663,10 @@
                rockchip,pmu = <&pmu>;
                rockchip,sgrf = <&sgrf>;
                rockchip,noc = <&noc>;
-               reg = <0xff610000 0x3fc
-                      0xff620000 0x294
-                      0xff630000 0x3fc
-                      0xff640000 0x294>;
+               reg = <0x0 0xff610000 0x0 0x3fc
+                      0x0 0xff620000 0x0 0x294
+                      0x0 0xff630000 0x0 0x3fc
+                      0x0 0xff640000 0x0 0x294>;
                rockchip,sram = <&ddr_sram>;
                clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
                         <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
@@ -678,7 +678,7 @@
 
        i2c2: i2c@ff660000 {
                compatible = "rockchip,rk3288-i2c";
-               reg = <0xff660000 0x1000>;
+               reg = <0x0 0xff660000 0x0 0x1000>;
                interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -691,7 +691,7 @@
 
        pwm0: pwm@ff680000 {
                compatible = "rockchip,rk3288-pwm";
-               reg = <0xff680000 0x10>;
+               reg = <0x0 0xff680000 0x0 0x10>;
                #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm0_pin>;
@@ -702,7 +702,7 @@
 
        pwm1: pwm@ff680010 {
                compatible = "rockchip,rk3288-pwm";
-               reg = <0xff680010 0x10>;
+               reg = <0x0 0xff680010 0x0 0x10>;
                #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm1_pin>;
@@ -713,7 +713,7 @@
 
        pwm2: pwm@ff680020 {
                compatible = "rockchip,rk3288-pwm";
-               reg = <0xff680020 0x10>;
+               reg = <0x0 0xff680020 0x0 0x10>;
                #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm2_pin>;
@@ -724,7 +724,7 @@
 
        pwm3: pwm@ff680030 {
                compatible = "rockchip,rk3288-pwm";
-               reg = <0xff680030 0x10>;
+               reg = <0x0 0xff680030 0x0 0x10>;
                #pwm-cells = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm3_pin>;
@@ -735,10 +735,10 @@
 
        bus_intmem@ff700000 {
                compatible = "mmio-sram";
-               reg = <0xff700000 0x18000>;
+               reg = <0x0 0xff700000 0x0 0x18000>;
                #address-cells = <1>;
                #size-cells = <1>;
-               ranges = <0 0xff700000 0x18000>;
+               ranges = <0 0x0 0xff700000 0x18000>;
                smp-sram@0 {
                        compatible = "rockchip,rk3066-smp-sram";
                        reg = <0x00 0x10>;
@@ -751,82 +751,82 @@
 
        sram@ff720000 {
                compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
-               reg = <0xff720000 0x1000>;
+               reg = <0x0 0xff720000 0x0 0x1000>;
        };
 
        qos_gpu_r: qos@ffaa0000 {
                compatible = "syscon";
-               reg = <0xffaa0000 0x20>;
+               reg = <0x0 0xffaa0000 0x0 0x20>;
        };
 
        qos_gpu_w: qos@ffaa0080 {
                compatible = "syscon";
-               reg = <0xffaa0080 0x20>;
+               reg = <0x0 0xffaa0080 0x0 0x20>;
        };
 
        qos_vio1_vop: qos@ffad0000 {
                compatible = "syscon";
-               reg = <0xffad0000 0x20>;
+               reg = <0x0 0xffad0000 0x0 0x20>;
        };
 
        qos_vio1_isp_w0: qos@ffad0100 {
                compatible = "syscon";
-               reg = <0xffad0100 0x20>;
+               reg = <0x0 0xffad0100 0x0 0x20>;
        };
 
        qos_vio1_isp_w1: qos@ffad0180 {
                compatible = "syscon";
-               reg = <0xffad0180 0x20>;
+               reg = <0x0 0xffad0180 0x0 0x20>;
        };
 
        qos_vio0_vop: qos@ffad0400 {
                compatible = "syscon";
-               reg = <0xffad0400 0x20>;
+               reg = <0x0 0xffad0400 0x0 0x20>;
        };
 
        qos_vio0_vip: qos@ffad0480 {
                compatible = "syscon";
-               reg = <0xffad0480 0x20>;
+               reg = <0x0 0xffad0480 0x0 0x20>;
        };
 
        qos_vio0_iep: qos@ffad0500 {
                compatible = "syscon";
-               reg = <0xffad0500 0x20>;
+               reg = <0x0 0xffad0500 0x0 0x20>;
        };
 
        qos_vio2_rga_r: qos@ffad0800 {
                compatible = "syscon";
-               reg = <0xffad0800 0x20>;
+               reg = <0x0 0xffad0800 0x0 0x20>;
        };
 
        qos_vio2_rga_w: qos@ffad0880 {
                compatible = "syscon";
-               reg = <0xffad0880 0x20>;
+               reg = <0x0 0xffad0880 0x0 0x20>;
        };
 
        qos_vio1_isp_r: qos@ffad0900 {
                compatible = "syscon";
-               reg = <0xffad0900 0x20>;
+               reg = <0x0 0xffad0900 0x0 0x20>;
        };
 
        qos_video: qos@ffae0000 {
                compatible = "syscon";
-               reg = <0xffae0000 0x20>;
+               reg = <0x0 0xffae0000 0x0 0x20>;
        };
 
        qos_hevc_r: qos@ffaf0000 {
                compatible = "syscon";
-               reg = <0xffaf0000 0x20>;
+               reg = <0x0 0xffaf0000 0x0 0x20>;
        };
 
        qos_hevc_w: qos@ffaf0080 {
                compatible = "syscon";
-               reg = <0xffaf0080 0x20>;
+               reg = <0x0 0xffaf0080 0x0 0x20>;
        };
 
        pmu: power-management@ff730000 {
                compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
-               reg = <0xff730000 0x100>;
+               reg = <0x0 0xff730000 0x0 0x100>;
 
                power: power-controller {
                        compatible = "rockchip,rk3288-power-controller";
@@ -945,12 +945,12 @@
 
        sgrf: syscon@ff740000 {
                compatible = "rockchip,rk3288-sgrf", "syscon";
-               reg = <0xff740000 0x1000>;
+               reg = <0x0 0xff740000 0x0 0x1000>;
        };
 
        cru: clock-controller@ff760000 {
                compatible = "rockchip,rk3288-cru";
-               reg = <0xff760000 0x1000>;
+               reg = <0x0 0xff760000 0x0 0x1000>;
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
@@ -968,7 +968,7 @@
 
        grf: syscon@ff770000 {
                compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
-               reg = <0xff770000 0x1000>;
+               reg = <0x0 0xff770000 0x0 0x1000>;
 
                edp_phy: edp-phy {
                        compatible = "rockchip,rk3288-dp-phy";
@@ -1021,7 +1021,7 @@
 
        wdt: watchdog@ff800000 {
                compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
-               reg = <0xff800000 0x100>;
+               reg = <0x0 0xff800000 0x0 0x100>;
                clocks = <&cru PCLK_WDT>;
                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -1029,7 +1029,7 @@
 
        spdif: sound@ff8b0000 {
                compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
-               reg = <0xff8b0000 0x10000>;
+               reg = <0x0 0xff8b0000 0x0 0x10000>;
                #sound-dai-cells = <0>;
                clock-names = "hclk", "mclk";
                clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
@@ -1044,7 +1044,7 @@
 
        i2s: i2s@ff890000 {
                compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
-               reg = <0xff890000 0x10000>;
+               reg = <0x0 0xff890000 0x0 0x10000>;
                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -1062,7 +1062,7 @@
        cif_isp0: cif_isp@ff910000 {
                compatible = "rockchip,rk3288-cif-isp";
                rockchip,grf = <&grf>;
-               reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
+               reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x4000>;
                reg-names = "register", "csihost-register";
                clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
                        <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
@@ -1081,7 +1081,7 @@
 
        isp: isp@ff910000 {
                compatible = "rockchip,rk3288-isp", "rockchip,isp";
-               reg = <0xff910000 0x4000>;
+               reg = <0x0 0xff910000 0x0 0x4000>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                power-domains = <&power RK3288_PD_VIO>;
                clocks =
@@ -1121,7 +1121,7 @@
 
        isp_mmu: iommu@ff914000 {
                compatible = "rockchip,iommu";
-               reg = <0xff914000 0x100>, <0xff915000 0x100>;
+               reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "isp_mmu";
                clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
@@ -1134,7 +1134,7 @@
 
        rga: rga@ff920000 {
                compatible = "rockchip,rk3288-rga";
-               reg = <0xff920000 0x180>;
+               reg = <0x0 0xff920000 0x0 0x180>;
                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "rga";
                clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
@@ -1148,7 +1148,7 @@
 
        vopb: vop@ff930000 {
                compatible = "rockchip,rk3288-vop";
-               reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
+               reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1186,7 +1186,7 @@
 
        vopb_mmu: iommu@ff930300 {
                compatible = "rockchip,iommu";
-               reg = <0xff930300 0x100>;
+               reg = <0x0 0xff930300 0x0 0x100>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vopb_mmu";
                clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
@@ -1198,7 +1198,7 @@
 
        vopl: vop@ff940000 {
                compatible = "rockchip,rk3288-vop";
-               reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
+               reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1237,7 +1237,7 @@
 
        vopl_mmu: iommu@ff940300 {
                compatible = "rockchip,iommu";
-               reg = <0xff940300 0x100>;
+               reg = <0x0 0xff940300 0x0 0x100>;
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vopl_mmu";
                clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
@@ -1249,7 +1249,7 @@
 
        mipi_dsi: mipi@ff960000 {
                compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
-               reg = <0xff960000 0x4000>;
+               reg = <0x0 0xff960000 0x0 0x4000>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
                clock-names = "ref", "pclk";
@@ -1277,7 +1277,7 @@
 
        edp: dp@ff970000 {
                compatible = "rockchip,rk3288-dp";
-               reg = <0xff970000 0x4000>;
+               reg = <0x0 0xff970000 0x0 0x4000>;
                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
                clock-names = "dp", "pclk";
@@ -1310,7 +1310,7 @@
 
        lvds: lvds@ff96c000 {
                compatible = "rockchip,rk3288-lvds";
-               reg = <0xff96c000 0x4000>;
+               reg = <0x0 0xff96c000 0x0 0x4000>;
                clocks = <&cru PCLK_LVDS_PHY>;
                clock-names = "pclk_lvds";
                pinctrl-names = "default";
@@ -1343,7 +1343,7 @@
 
        hdmi: hdmi@ff980000 {
                compatible = "rockchip,rk3288-dw-hdmi";
-               reg = <0xff980000 0x20000>;
+               reg = <0x0 0xff980000 0x0 0x20000>;
                reg-io-width = <4>;
                rockchip,grf = <&grf>;
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
@@ -1372,7 +1372,7 @@
 
        vpu: video-codec@ff9a0000 {
                compatible = "rockchip,rk3288-vpu";
-               reg = <0xff9a0000 0x800>;
+               reg = <0x0 0xff9a0000 0x0 0x800>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vepu", "vdpu";
@@ -1387,7 +1387,7 @@
 
        vpu_service: vpu-service@ff9a0000 {
                compatible = "rockchip,vpu_service";
-               reg = <0xff9a0000 0x800>;
+               reg = <0x0 0xff9a0000 0x0 0x800>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "irq_enc", "irq_dec";
@@ -1406,7 +1406,7 @@
 
        vpu_mmu: iommu@ff9a0800 {
                compatible = "rockchip,iommu";
-               reg = <0xff9a0800 0x100>;
+               reg = <0x0 0xff9a0800 0x0 0x100>;
                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vpu_mmu";
                clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
@@ -1417,7 +1417,7 @@
 
        hevc_service: hevc-service@ff9c0000 {
                compatible = "rockchip,hevc_service";
-               reg = <0xff9c0000 0x400>;
+               reg = <0x0 0xff9c0000 0x0 0x400>;
                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "irq_dec";
                clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
@@ -1448,7 +1448,7 @@
 
        hevc_mmu: iommu@ff9c0440 {
                compatible = "rockchip,iommu";
-               reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+               reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "hevc_mmu";
                clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
@@ -1465,7 +1465,7 @@
                             "arm,malit76x",
                             "arm,malit7xx",
                             "arm,mali-midgard";
-               reg = <0xffa30000 0x10000>;
+               reg = <0x0 0xffa30000 0x0 0x10000>;
                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -1518,12 +1518,12 @@
 
        noc: syscon@ffac0000 {
                compatible = "rockchip,rk3288-noc", "syscon";
-               reg = <0xffac0000 0x2000>;
+               reg = <0x0 0xffac0000 0x0 0x2000>;
        };
 
        efuse: efuse@ffb40000 {
                compatible = "rockchip,rockchip-efuse";
-               reg = <0xffb40000 0x20>;
+               reg = <0x0 0xffb40000 0x0 0x20>;
                #address-cells = <1>;
                #size-cells = <1>;
                clocks = <&cru PCLK_EFUSE256>;
@@ -1540,10 +1540,10 @@
                #interrupt-cells = <3>;
                #address-cells = <0>;
 
-               reg = <0xffc01000 0x1000>,
-                     <0xffc02000 0x2000>,
-                     <0xffc04000 0x2000>,
-                     <0xffc06000 0x2000>;
+               reg = <0x0 0xffc01000 0x0 0x1000>,
+                     <0x0 0xffc02000 0x0 0x2000>,
+                     <0x0 0xffc04000 0x0 0x2000>,
+                     <0x0 0xffc06000 0x0 0x2000>;
                interrupts = <GIC_PPI 9 0xf04>;
        };
 
@@ -1551,13 +1551,13 @@
                compatible = "rockchip,rk3288-pinctrl";
                rockchip,grf = <&grf>;
                rockchip,pmu = <&pmu>;
-               #address-cells = <1>;
-               #size-cells = <1>;
+               #address-cells = <2>;
+               #size-cells = <2>;
                ranges;
 
                gpio0: gpio0@ff750000 {
                        compatible = "rockchip,gpio-bank";
-                       reg =   <0xff750000 0x100>;
+                       reg = <0x0 0xff750000 0x0 0x100>;
                        interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO0>;
 
@@ -1570,7 +1570,7 @@
 
                gpio1: gpio1@ff780000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff780000 0x100>;
+                       reg = <0x0 0xff780000 0x0 0x100>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO1>;
 
@@ -1583,7 +1583,7 @@
 
                gpio2: gpio2@ff790000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff790000 0x100>;
+                       reg = <0x0 0xff790000 0x0 0x100>;
                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO2>;
 
@@ -1596,7 +1596,7 @@
 
                gpio3: gpio3@ff7a0000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff7a0000 0x100>;
+                       reg = <0x0 0xff7a0000 0x0 0x100>;
                        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO3>;
 
@@ -1609,7 +1609,7 @@
 
                gpio4: gpio4@ff7b0000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff7b0000 0x100>;
+                       reg = <0x0 0xff7b0000 0x0 0x100>;
                        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO4>;
 
@@ -1622,7 +1622,7 @@
 
                gpio5: gpio5@ff7c0000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff7c0000 0x100>;
+                       reg = <0x0 0xff7c0000 0x0 0x100>;
                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO5>;
 
@@ -1635,7 +1635,7 @@
 
                gpio6: gpio6@ff7d0000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff7d0000 0x100>;
+                       reg = <0x0 0xff7d0000 0x0 0x100>;
                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO6>;
 
@@ -1648,7 +1648,7 @@
 
                gpio7: gpio7@ff7e0000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff7e0000 0x100>;
+                       reg = <0x0 0xff7e0000 0x0 0x100>;
                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO7>;
 
@@ -1661,7 +1661,7 @@
 
                gpio8: gpio8@ff7f0000 {
                        compatible = "rockchip,gpio-bank";
-                       reg = <0xff7f0000 0x100>;
+                       reg = <0x0 0xff7f0000 0x0 0x100>;
                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cru PCLK_GPIO8>;