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80 col violation.
author
Evan Cheng
<evan.cheng@apple.com>
Sat, 11 Jul 2009 06:37:27 +0000
(06:37 +0000)
committer
Evan Cheng
<evan.cheng@apple.com>
Sat, 11 Jul 2009 06:37:27 +0000
(06:37 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMBaseInstrInfo.cpp
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diff --git
a/lib/Target/ARM/ARMBaseInstrInfo.cpp
b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index f7e634a48cc4ced67579bdf9fa1a8d5798df1374..d7ba73c3e4bf80c7d2eb33ddf04ffbec6943bdfc 100644
(file)
--- a/
lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/
lib/Target/ARM/ARMBaseInstrInfo.cpp
@@
-588,8
+588,8
@@
ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
}
if (DestRC == ARM::GPRRegisterClass)
- AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
DestReg)
- .addReg(SrcReg)));
+ AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
+
DestReg)
.addReg(SrcReg)));
else if (DestRC == ARM::SPRRegisterClass)
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYS)), DestReg)
.addReg(SrcReg));