1) clock clk_vio0_noc would cause mipi lcdc no display on 3368h, remove it.
*v0.0x21.0xb:
1) some log is boring, so set print level more high.
+*v0.0x21.0xc:
+ 1) support rk3288.
*/
-#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x21, 0xb)
+#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x21, 0xc)
#define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys"
#define CAMSYS_PLATFORM_MARVIN_NAME "Platform_MarvinDev"
}
}
} else{
- mrv_clk->pd_isp =
- devm_clk_get(&pdev->dev, "pd_isp");
+ /*mrv_clk->pd_isp = */
+ /* devm_clk_get(&pdev->dev, "pd_isp");*/
mrv_clk->aclk_isp =
devm_clk_get(&pdev->dev, "aclk_isp");
mrv_clk->hclk_isp =
mrv_clk->clk_mipi_24m =
devm_clk_get(&pdev->dev, "clk_mipi_24m");
- if (IS_ERR_OR_NULL(mrv_clk->pd_isp) ||
+ if (
+ /*IS_ERR_OR_NULL(mrv_clk->pd_isp) ||*/
IS_ERR_OR_NULL(mrv_clk->aclk_isp) ||
IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
IS_ERR_OR_NULL(mrv_clk->isp) ||
}
- if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || CHIP_TYPE == 3399) {
+ if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 ||
+ CHIP_TYPE == 3399 || CHIP_TYPE == 3288) {
if (CHIP_TYPE == 3399) {
camsys_dev->dsiphy_reg =
kzalloc(sizeof(camsys_meminfo_t), GFP_KERNEL);
if (camsys_dev->dsiphy_reg == NULL) {
camsys_err("malloc camsys_meminfo_t for dsiphy_reg failed!");
+ err = -ENOMEM;
+ goto fail;
}
if (of_property_read_u32_array(
kzalloc(sizeof(camsys_meminfo_t), GFP_KERNEL);
if (camsys_dev->csiphy_reg == NULL) {
camsys_err("malloc camsys_meminfo_t for csiphy_reg failed!");
+ err = -ENOMEM;
+ goto fail;
}
if (of_property_read_u32_array(
static camsys_soc_priv_t *camsys_soc_p;
-extern int camsys_rk3288_cfg(
- camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
+#ifdef CONFIG_ARM64
extern int camsys_rk3368_cfg(
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
extern int camsys_rk3366_cfg(
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
extern int camsys_rk3399_cfg(
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
+#else
+extern int camsys_rk3288_cfg(
+ camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
+#endif
camsys_soc_priv_t *camsys_soc_get(void)
{
if (camsys_soc_p != NULL) {
goto fail;
}
+#ifdef CONFIG_ARM64
if (chip_type == 3368) {
strlcpy(camsys_soc_p->name, "camsys_rk3368", 31);
camsys_soc_p->soc_cfg = camsys_rk3368_cfg;
- camsys_trace(2, "camsys_soc_init exit!");
- } else if (chip_type == 3288) {
- if (cpu_is_rk3288()) {
- strlcpy(camsys_soc_p->name, "camsys_rk3288", 31);
- camsys_soc_p->soc_cfg = camsys_rk3288_cfg;
- } else {
- camsys_err("camsys isn't support soc!");
- goto fail;
- }
+ camsys_trace(2, "rk3368 exit!");
} else if (chip_type == 3366) {
strlcpy(camsys_soc_p->name, "camsys_rk3366", 31);
camsys_soc_p->soc_cfg = camsys_rk3366_cfg;
- camsys_trace(2, "camsys_soc_init exit!");
+ camsys_trace(2, "rk3366 exit!");
} else if (chip_type == 3399) {
strlcpy(camsys_soc_p->name, "camsys_rk3399", 31);
camsys_soc_p->soc_cfg = camsys_rk3399_cfg;
- camsys_trace(2, "camsys_soc_init exit!");
+ camsys_trace(2, "rk3399 exit!");
+ }
+#else
+ if (chip_type == 3288) {
+ strlcpy(camsys_soc_p->name, "camsys_rk3288", 31);
+ camsys_soc_p->soc_cfg = camsys_rk3288_cfg;
+ camsys_trace(2, "rk3288 exit!");
}
+#endif
return 0;
fail:
static int camsys_rk3288_mipiphy0_wr_reg(
-unsigned char addr, unsigned char data)
+unsigned char addr, unsigned char data, camsys_mipiphy_soc_para_t *para)
{
/*TESTCLK=1*/
write_grf_reg(GRF_SOC_CON14_OFFSET,
/*set clock lane*/
camsys_rk3288_mipiphy0_wr_reg
- (0x34, 0x15);
+ (0x34, 0x15, para);
if (para->phy->data_en_bit >= 0x00)
camsys_rk3288_mipiphy0_wr_reg
- (0x44, hsfreqrange);
+ (0x44, hsfreqrange, para);
if (para->phy->data_en_bit >= 0x01)
camsys_rk3288_mipiphy0_wr_reg(
- 0x54, hsfreqrange);
+ 0x54, hsfreqrange, para);
if (para->phy->data_en_bit >= 0x04) {
camsys_rk3288_mipiphy0_wr_reg
- (0x84, hsfreqrange);
+ (0x84, hsfreqrange, para);
camsys_rk3288_mipiphy0_wr_reg
- (0x94, hsfreqrange);
+ (0x94, hsfreqrange, para);
}
/*Normal operation*/
- camsys_rk3288_mipiphy0_wr_reg(0x0, -1);
+ camsys_rk3288_mipiphy0_wr_reg(0x0, -1, para);
/*TESTCLK=1*/
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX0_TESTCLK_MASK
return -1;
}
+#define MRV_AFM_BASE 0x0000
+#define VI_IRCL 0x0014
+
int camsys_rk3288_cfg(
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
{
case Clk_DriverStrength_Cfg: {
para_int = (unsigned int *)cfg_para;
__raw_writel((((*para_int) & 0x03) << 3)|(0x03 << 3),
- RK_GRF_VIRT + 0x01d4);
+ (void *)(camsys_dev->rk_grf_base + 0x01d4));
break;
}
/* 1.8v IO*/
__raw_writel
(((1 << 1) | (1 << (1 + 16))),
- RK_GRF_VIRT + 0x0380);
+ (void *)(camsys_dev->rk_grf_base + 0x0380));
} else {
/* 3.3v IO*/
__raw_writel
(((0 << 1) | (1 << (1 + 16))),
- RK_GRF_VIRT + 0x0380);
+ (void *)(camsys_dev->rk_grf_base + 0x0380));
}
break;
}
unsigned int reset;
reset = (unsigned int)cfg_para;
-
+ /*
if (reset == 1)
cru_writel(0x40004000, 0x1d0);
else
cru_writel(0x40000000, 0x1d0);
camsys_trace(2, "Isp_SoftRst: %d", reset);
break;
+ */
+ if (reset == 1)
+ __raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
+ MRV_AFM_BASE + VI_IRCL));
+ else
+ __raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
+ MRV_AFM_BASE + VI_IRCL));
+ camsys_trace(2, "Isp self soft rst: %d", reset);
+ break;
}
default: {
#define CSIHOST_ERR2 (0x24)
#define write_grf_reg(addr, val) \
- __raw_writel(val, addr + RK_GRF_VIRT)
+ __raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
#define read_grf_reg(addr) \
- __raw_readl(addr + RK_GRF_VIRT)
+ __raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
#define mask_grf_reg(addr, msk, val) \
write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
#ifdef CONFIG_ARM64