Moved RegClassIDs enum to be next to the RegTypes enum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7114 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index 8fcf7dba0bcf3ef13ce09d884c301c4601c6f701..47885a4f578b13331c35e078cb66bc27a5633266 100644 (file)
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -249,20 +249,6 @@ struct UltraSparcInstrInfo : public TargetInstrInfo {
 //----------------------------------------------------------------------------
 
 class UltraSparcRegInfo : public TargetRegInfo {
-public:
-  // The actual register classes in the Sparc
-  //
-  // **** WARNING: If this enum order is changed, also modify 
-  // getRegisterClassOfValue method below since it assumes this particular 
-  // order for efficiency.
-  // 
-  enum RegClassIDs { 
-    IntRegClassID,                      // Integer
-    FloatRegClassID,                    // Float (both single/double)
-    IntCCRegClassID,                    // Int Condition Code
-    FloatCCRegClassID,                  // Float Condition code
-    SpecialRegClassID                   // Special (unallocated) registers
-  };
 
 private:
 
@@ -328,6 +314,20 @@ public:
     SpecialRegType
   };
 
+  // The actual register classes in the Sparc
+  //
+  // **** WARNING: If this enum order is changed, also modify 
+  // getRegisterClassOfValue method below since it assumes this particular 
+  // order for efficiency.
+  // 
+  enum RegClassIDs { 
+    IntRegClassID,                      // Integer
+    FloatRegClassID,                    // Float (both single/double)
+    IntCCRegClassID,                    // Int Condition Code
+    FloatCCRegClassID,                  // Float Condition code
+    SpecialRegClassID                   // Special (unallocated) registers
+  };
+
   UltraSparcRegInfo(const UltraSparc &tgt);
 
   // To find the register class used for a specified Type