#include <asm/io.h>
#include <asm/apm.h>
#include <asm/adc.h>
-#include <asm/hp6xx/hp6xx.h>
+#include <asm/hp6xx.h>
#define SH7709_PGDR 0xa400012c
#include <linux/time.h>
#include <asm/io.h>
#include <asm/hd64461.h>
-#include <asm/hp6xx/hp6xx.h>
+#include <asm/hp6xx.h>
#include <asm/cpu/dac.h>
#include <asm/pm.h>
#include <asm/hd64461.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/hp6xx/hp6xx.h>
+#include <asm/hp6xx.h>
#include <asm/cpu/dac.h>
#define SCPCR 0xa4000116
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/io.h>
-#include <asm/hs7751rvoip/hs7751rvoip.h>
+#include <asm/hs7751rvoip.h>
#include <asm/addrspace.h>
extern void *area6_io8_base; /* Area 6 8bit I/O Base address */
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/hs7751rvoip/hs7751rvoip.h>
+#include <asm/hs7751rvoip.h>
static int mask_pos[] = {8, 9, 10, 11, 12, 13, 0, 1, 2, 3, 4, 5, 6, 7};
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/hdreg.h>
-#include <linux/ide.h>
#include <linux/pm.h>
+#include <asm/hs7751rvoip.h>
#include <asm/io.h>
-#include <asm/hs7751rvoip/hs7751rvoip.h>
#include <asm/machvec.h>
-#include <asm/rtc.h>
-#include <asm/irq.h>
static void __init hs7751rvoip_init_irq(void)
{
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/types.h>
-#include <asm/r7780rp/r7780rp.h>
+#include <asm/r7780rp.h>
#include <asm/addrspace.h>
#include <asm/io.h>
*/
#include <linux/init.h>
#include <linux/irq.h>
-#include <asm/io.h>
+#include <linux/io.h>
+#include <asm/r7780rp.h>
#ifdef CONFIG_SH_R7780MP
static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
}
static struct irq_chip r7780rp_irq_chip __read_mostly = {
- .name = "r7780rp",
+ .name = "R7780RP",
.mask = disable_r7780rp_irq,
.unmask = enable_r7780rp_irq,
.mask_ack = disable_r7780rp_irq,
for (i = 0; i < 15; i++) {
disable_irq_nosync(i);
- set_irq_chip_and_handler(i, &r7780rp_irq_chip,
- handle_level_irq);
+ set_irq_chip_and_handler_name(i, &r7780rp_irq_chip,
+ handle_level_irq, "level");
enable_r7780rp_irq(i);
}
}
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
-#include <asm/r7780rp/r7780rp.h>
+#include <asm/r7780rp.h>
#include <asm/clock.h>
#include <asm/io.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
-#include <asm/rts7751r2d/rts7751r2d.h>
-#include <asm/io.h>
+#include <linux/io.h>
+#include <asm/rts7751r2d.h>
#include <asm/addrspace.h>
/*
* Modified for RTS7751R2D by
* Atom Create Engineering Co., Ltd. 2002.
*/
-
#include <linux/init.h>
#include <linux/irq.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/rts7751r2d/rts7751r2d.h>
+#include <linux/io.h>
+#include <asm/rts7751r2d.h>
#if defined(CONFIG_RTS7751R2D_REV11)
static int mask_pos[] = {11, 9, 8, 12, 10, 6, 5, 4, 7, 14, 13, 0, 0, 0, 0};
*
* This file contains Renesas Technology Sales RTS7751R2D specific LED code.
*/
-
-#include <asm/io.h>
-#include <asm/rts7751r2d/rts7751r2d.h>
-
-#ifdef CONFIG_HEARTBEAT
-
+#include <linux/io.h>
#include <linux/sched.h>
+#include <asm/rts7751r2d.h>
/* Cycle the LED's in the clasic Knightriger/Sun pattern */
void heartbeat_rts7751r2d(void)
else
bit--;
}
-#endif /* CONFIG_HEARTBEAT */
-
-void rts7751r2d_led(unsigned short value)
-{
- ctrl_outw(value, PA_OUTPORT);
-}
-
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/pm.h>
-#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/mach/rts7751r2d.h>
+#include <asm/io.h>
#include <asm/voyagergx.h>
extern void heartbeat_rts7751r2d(void);
*/
#include <linux/init.h>
#include <asm/machvec.h>
-#include <asm/shmin/shmin.h>
+#include <asm/shmin.h>
#include <asm/clock.h>
#include <asm/irq.h>
#include <asm/io.h>
Copyright 2003 (c) Lineo uSolutions,Inc.
*/
-/* -------------------------------------------------------------------- */
-
-#undef DEBUG
-
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/init.h>
-#include <linux/irq.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <linux/io.h>
#include <asm/voyagergx.h>
+#include <asm/rts7751r2d.h>
static void disable_voyagergx_irq(unsigned int irq)
{
unsigned long val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
- pr_debug("disable_voyagergx_irq(%d): mask=%x\n", irq, mask);
+ pr_debug("disable_voyagergx_irq(%d): mask=%lx\n", irq, mask);
val = inl(VOYAGER_INT_MASK);
val &= ~mask;
outl(val, VOYAGER_INT_MASK);
unsigned long val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
- pr_debug("disable_voyagergx_irq(%d): mask=%x\n", irq, mask);
+ pr_debug("disable_voyagergx_irq(%d): mask=%lx\n", irq, mask);
val = inl(VOYAGER_INT_MASK);
val |= mask;
outl(val, VOYAGER_INT_MASK);
} else {
printk("Unexpected IRQ irq = %d status = 0x%08lx\n", irq, val);
}
- pr_debug("voyagergx_irq_demux %d \n", i);
+ pr_debug("voyagergx_irq_demux %ld\n", i);
#else
for (bit = 1, i = 0 ; i < VOYAGER_IRQ_NUM ; bit <<= 1, i++)
if (val & bit)
setup_irq(IRQ_VOYAGER, &irq0);
}
-
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
-#include <asm/r7780rp/r7780rp.h>
+#include <asm/r7780rp.h>
#include <asm/io.h>
#include "pci-sh4.h"
*
* PCI initialization for the Renesas SH7751R RTS7751R2D board
*/
-
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
-#include <linux/delay.h>
#include <linux/pci.h>
-#include <linux/module.h>
-#include <asm/rts7751r2d/rts7751r2d.h>
-#include <asm/io.h>
+#include <linux/io.h>
+#include <asm/rts7751r2d.h>
#include "pci-sh4.h"
+static u8 rts7751r2d_irq_tab[] __initdata = {
+ IRQ_PCISLOT1,
+ IRQ_PCISLOT2,
+ IRQ_PCMCIA,
+ IRQ_PCIETH,
+};
+
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
- switch (slot) {
- case 0: return IRQ_PCISLOT1; /* PCI Extend slot #1 */
- case 1: return IRQ_PCISLOT2; /* PCI Extend slot #2 */
- case 2: return IRQ_PCMCIA; /* PCI Cardbus Bridge */
- case 3: return IRQ_PCIETH; /* Realtek Ethernet controller */
- default:
- printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
- return -1;
- }
+ return rts7751r2d_irq_tab[slot];
}
static struct resource sh7751_io_resource = {
* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
*/
#include <linux/kernel.h>
-#include <linux/init.h>
#include <linux/irq.h>
+#include <linux/io.h>
#include <asm/system.h>
-#include <asm/io.h>
static void disable_intc2_irq(unsigned int irq)
{
}
static struct irq_chip intc2_irq_chip = {
- .typename = "intc2",
+ .name = "INTC2",
.mask = disable_intc2_irq,
.unmask = enable_intc2_irq,
.mask_ack = disable_intc2_irq,
* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
* would be: ^ ^ ^ ^
* | | | |
- * make_intc2_irq(84, 0, 16, 0, 13);
+ * { 84, 0, 16, 0, 13 },
+ *
+ * in the intc2_data table.
*/
-void make_intc2_irq(struct intc2_data *p)
+void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
{
- unsigned int flags;
- unsigned long ipr;
-
- disable_irq_nosync(p->irq);
-
- /* Set the priority level */
- local_irq_save(flags);
-
- ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
- ipr &= ~(0xf << p->ipr_shift);
- ipr |= p->priority << p->ipr_shift;
- ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
-
- local_irq_restore(flags);
+ int i;
- set_irq_chip_and_handler(p->irq, &intc2_irq_chip, handle_level_irq);
- set_irq_chip_data(p->irq, p);
+ for (i = 0; i < nr_irqs; i++) {
+ unsigned long ipr, flags;
+ struct intc2_data *p = table + i;
- enable_intc2_irq(p->irq);
-}
+ disable_irq_nosync(p->irq);
-static struct intc2_data intc2_irq_table[] = {
-#if defined(CONFIG_CPU_SUBTYPE_ST40)
- {64, 0, 0, 0, 0, 13}, /* PCI serr */
- {65, 0, 4, 0, 1, 13}, /* PCI err */
- {66, 0, 4, 0, 2, 13}, /* PCI ad */
- {67, 0, 4, 0, 3, 13}, /* PCI pwd down */
- {72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
- {73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
- {74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
- {75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
- {76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
- {78, 0, 8, 0, 11, 13}, /* DMAC ERR */
- {80, 0, 12, 0, 12, 13}, /* PIO0 */
- {84, 0, 16, 0, 13, 13}, /* PIO1 */
- {88, 0, 20, 0, 14, 13}, /* PIO2 */
- {112, 4, 0, 4, 0, 13}, /* Mailbox */
- #ifdef CONFIG_CPU_SUBTYPE_ST40GX1
- {116, 4, 4, 4, 4, 13}, /* SSC0 */
- {120, 4, 8, 4, 8, 13}, /* IR Blaster */
- {124, 4, 12, 4, 12, 13}, /* USB host */
- {128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
- {132, 4, 20, 4, 20, 13}, /* UART0 */
- {134, 4, 20, 4, 22, 13}, /* UART2 */
- {136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
- {140, 4, 28, 4, 28, 13}, /* EMPI */
- {144, 8, 0, 8, 0, 13}, /* MAFE */
- {148, 8, 4, 8, 4, 13}, /* PWM */
- {152, 8, 8, 8, 8, 13}, /* SSC1 */
- {156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
- {160, 8, 16, 8, 16, 13}, /* USB target */
- {164, 8, 20, 8, 20, 13}, /* UART1 */
- {168, 8, 24, 8, 24, 13}, /* Teletext */
- {172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
- {173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
- {174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
-#endif
-#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
-/*
- * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
- */
- /* INTPRIO0 | INTMSK0 */
- {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
- {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
- {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
- {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
- /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
- /* INTPRIO4 | INTMSK0 */
- {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
- {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
- {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
- {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
- {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
- {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
- {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
- {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
- /* INTPRIO8 | INTMSK0 */
- {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
- {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
- {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
- {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
- {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
- {65, 8, 24, 0, 16, 3}, /* LCDC */
- /* 66, 67 unused */
- {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
- {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
- {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
- /* 71 unused */
- {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
- {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
- {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
- {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
- {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
- {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
- {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
- {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
- /* | INTMSK4 */
- {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
- {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
- {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
- {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
- {84, 8, 0, 4, 19, 3}, /* HSPII */
- /* INTPRIOC | INTMSK4 */
- /* 85-87 unused/reserved */
- {88, 12, 20, 4, 18, 3}, /* MMCI0 */
- {89, 12, 20, 4, 17, 3}, /* MMCI1 */
- {90, 12, 20, 4, 16, 3}, /* MMCI2 */
- {91, 12, 20, 4, 15, 3}, /* MMCI3 */
- {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
- /* 93-107 reserved/undocumented */
- {108,12, 4, 4, 1, 3}, /* ADC */
- {109,12, 0, 4, 0, 3}, /* CMTI */
- /* 110-111 reserved/unused */
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
- { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
- { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
- { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
- { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
- { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
- { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
- { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
- { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
+ /* Set the priority level */
+ local_irq_save(flags);
- { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
- { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
- { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
- { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
+ ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET +
+ p->ipr_offset);
+ ipr &= ~(0xf << p->ipr_shift);
+ ipr |= p->priority << p->ipr_shift;
+ ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET +
+ p->ipr_offset);
- { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
- { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
- { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
- { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
- { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
-#endif
-};
+ local_irq_restore(flags);
-void __init init_IRQ_intc2(void)
-{
- int i;
+ set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip,
+ handle_level_irq, "level");
+ set_irq_chip_data(p->irq, p);
- for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++)
- make_intc2_irq(intc2_irq_table + i);
+ enable_intc2_irq(p->irq);
+ }
}
}
static struct irq_chip ipr_irq_chip = {
- .name = "ipr",
+ .name = "IPR",
.mask = disable_ipr_irq,
.unmask = enable_ipr_irq,
.mask_ack = disable_ipr_irq,
ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
ipr_data.priority = priority;
- set_irq_chip_and_handler(irq, &ipr_irq_chip, handle_level_irq);
+ set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
+ handle_level_irq, "level");
set_irq_chip_data(irq, &ipr_data);
enable_ipr_irq(irq);
* The SH-3 exception vector table.
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
- * Copyright (C) 2003 Paul Mundt
+ * Copyright (C) 2003 - 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
#endif
ENTRY(user_break_point_trap)
.long break_point_trap /* 1E0 */
+
+ /*
+ * Pad the remainder of the table out, exceptions residing in far
+ * away offsets can be manually inserted in to their appropriate
+ * location via set_exception_table_{evt,vec}().
+ */
+ .balign 4096,0,4096
* The SH-4 exception vector table.
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
- * Copyright (C) 2003 Paul Mundt
+ * Copyright (C) 2003 - 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
#endif
ENTRY(user_break_point_trap)
.long break_point_trap /* 1E0 */
+
+ /*
+ * Pad the remainder of the table out, exceptions residing in far
+ * away offsets can be manually inserted in to their appropriate
+ * location via set_exception_table_{evt,vec}().
+ */
+ .balign 4096,0,4096
ARRAY_SIZE(sh7760_devices));
}
__initcall(sh7760_devices_setup);
+
+/*
+ * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
+ */
+static struct intc2_data intc2_irq_table[] = {
+ /* INTPRIO0 | INTMSK0 */
+ {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
+ {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
+ {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
+ {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
+ /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
+ /* INTPRIO4 | INTMSK0 */
+ {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
+ {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
+ {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
+ {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
+ {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
+ {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
+ {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
+ {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
+ /* INTPRIO8 | INTMSK0 */
+ {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
+ {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
+ {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
+ {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
+ {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
+ {65, 8, 24, 0, 16, 3}, /* LCDC */
+ /* 66, 67 unused */
+ {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
+ {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
+ {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
+ /* 71 unused */
+ {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
+ {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
+ {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
+ {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
+ {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
+ {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
+ {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
+ {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
+ /* | INTMSK4 */
+ {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
+ {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
+ {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
+ {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
+ {84, 8, 0, 4, 19, 3}, /* HSPII */
+ /* INTPRIOC | INTMSK4 */
+ /* 85-87 unused/reserved */
+ {88, 12, 20, 4, 18, 3}, /* MMCI0 */
+ {89, 12, 20, 4, 17, 3}, /* MMCI1 */
+ {90, 12, 20, 4, 16, 3}, /* MMCI2 */
+ {91, 12, 20, 4, 15, 3}, /* MMCI3 */
+ {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
+ /* 93-107 reserved/undocumented */
+ {108,12, 4, 4, 1, 3}, /* ADC */
+ {109,12, 0, 4, 0, 3}, /* CMTI */
+ /* 110-111 reserved/unused */
+};
+
+void __init init_IRQ_intc2(void)
+{
+ make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
+}
ARRAY_SIZE(sh7780_devices));
}
__initcall(sh7780_devices_setup);
+
+static struct intc2_data intc2_irq_table[] = {
+ { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2 },
+ { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
+ { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
+ { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
+ { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
+ { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
+ { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
+ { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
+
+ { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
+ { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
+ { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
+ { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
+
+ { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
+ { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
+ { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
+ { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
+ { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
+};
+
+void __init init_IRQ_intc2(void)
+{
+ make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
+}
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
seq_printf(p, " %14s", irq_desc[i].chip->name);
- seq_printf(p, "-%s", handle_irq_name(irq_desc[i].handle_irq));
+ seq_printf(p, "-%-8s", irq_desc[i].name);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
{
printk("\n");
printk("Pid : %d, Comm: %20s\n", current->pid, current->comm);
- print_symbol("PC is at %s\n", regs->pc);
+ print_symbol("PC is at %s\n", instruction_pointer(regs));
printk("PC : %08lx SP : %08lx SR : %08lx ",
regs->pc, regs->regs[15], regs->sr);
#ifdef CONFIG_MMU
printk("MACH: %08lx MACL: %08lx GBR : %08lx PR : %08lx\n",
regs->mach, regs->macl, regs->gbr, regs->pr);
- /*
- * If we're in kernel mode, dump the stack too..
- */
- if (!user_mode(regs)) {
- extern void show_task(unsigned long *sp);
- unsigned long sp = regs->regs[15];
-
- show_task((unsigned long *)sp);
- }
+ show_trace(NULL, (unsigned long *)regs->regs[15], regs);
}
/*
-/* $Id: traps.c,v 1.17 2004/05/02 01:46:30 sugioka Exp $
- *
- * linux/arch/sh/traps.c
+/*
+ * 'traps.c' handles hardware traps and faults after we have saved some
+ * state in 'entry.S'.
*
* SuperH version: Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2000 Philipp Rumpf
* Copyright (C) 2000 David Howells
- * Copyright (C) 2002, 2003 Paul Mundt
- */
-
-/*
- * 'Traps.c' handles hardware traps and faults after we have saved some
- * state in 'entry.S'.
+ * Copyright (C) 2002 - 2006 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
*/
-#include <linux/sched.h>
#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
#include <linux/ptrace.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
#include <linux/init.h>
-#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-
+#include <linux/io.h>
#include <asm/system.h>
#include <asm/uaccess.h>
-#include <asm/io.h>
-#include <asm/atomic.h>
-#include <asm/processor.h>
-#include <asm/sections.h>
#ifdef CONFIG_SH_KGDB
#include <asm/kgdb.h>
#define TRAP_ILLEGAL_SLOT_INST 13
#endif
-/*
- * These constants are for searching for possible module text
- * segments. VMALLOC_OFFSET comes from mm/vmalloc.c; MODULE_RANGE is
- * a guess of how much space is likely to be vmalloced.
- */
-#define VMALLOC_OFFSET (8*1024*1024)
-#define MODULE_RANGE (8*1024*1024)
+static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
+{
+ unsigned long p;
+ int i;
+
+ printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
+
+ for (p = bottom & ~31; p < top; ) {
+ printk("%04lx: ", p & 0xffff);
+
+ for (i = 0; i < 8; i++, p += 4) {
+ unsigned int val;
+
+ if (p < bottom || p >= top)
+ printk(" ");
+ else {
+ if (__get_user(val, (unsigned int __user *)p)) {
+ printk("\n");
+ return;
+ }
+ printk("%08x ", val);
+ }
+ }
+ printk("\n");
+ }
+}
DEFINE_SPINLOCK(die_lock);
console_verbose();
spin_lock_irq(&die_lock);
+ bust_spinlocks(1);
+
printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
+
CHK_REMOTE_DEBUG(regs);
+ print_modules();
show_regs(regs);
+
+ printk("Process: %s (pid: %d, stack limit = %p)\n",
+ current->comm, current->pid, task_stack_page(current) + 1);
+
+ if (!user_mode(regs) || in_interrupt())
+ dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
+ (unsigned long)task_stack_page(current));
+
+ bust_spinlocks(0);
spin_unlock_irq(&die_lock);
do_exit(SIGSEGV);
}
-static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
+static inline void die_if_kernel(const char *str, struct pt_regs *regs,
+ long err)
{
if (!user_mode(regs))
die(str, regs, err);
*/
static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
{
- if (!user_mode(regs))
- {
+ if (!user_mode(regs)) {
const struct exception_table_entry *fixup;
fixup = search_exception_tables(regs->pc);
if (fixup) {
#define is_dsp_inst(regs) (0)
#endif /* CONFIG_SH_DSP */
-extern int do_fpu_inst(unsigned short, struct pt_regs*);
+/* arch/sh/kernel/cpu/sh4/fpu.c */
+extern int do_fpu_inst(unsigned short, struct pt_regs *);
+extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7, struct pt_regs regs);
asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7,
: "memory");
}
-void __init trap_init(void)
+void *set_exception_table_vec(unsigned int vec, void *handler)
{
extern void *exception_handling_table[];
+ void *old_handler;
+
+ old_handler = exception_handling_table[vec];
+ exception_handling_table[vec] = handler;
+ return old_handler;
+}
- exception_handling_table[TRAP_RESERVED_INST]
- = (void *)do_reserved_inst;
- exception_handling_table[TRAP_ILLEGAL_SLOT_INST]
- = (void *)do_illegal_slot_inst;
+void __init trap_init(void)
+{
+ set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
+ set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
defined(CONFIG_SH_FPU_EMU)
* reserved. They'll be handled in the math-emu case, or faulted on
* otherwise.
*/
- /* entry 64 corresponds to EXPEVT=0x800 */
- exception_handling_table[64] = (void *)do_reserved_inst;
- exception_handling_table[65] = (void *)do_illegal_slot_inst;
+ set_exception_table_evt(0x800, do_reserved_inst);
+ set_exception_table_evt(0x820, do_illegal_slot_inst);
+#elif defined(CONFIG_SH_FPU)
+ set_exception_table_evt(0x800, do_fpu_state_restore);
+ set_exception_table_evt(0x820, do_fpu_state_restore);
#endif
/* Setup VBR for boot cpu */
per_cpu_trap_init();
}
-void show_stack(struct task_struct *tsk, unsigned long *sp)
+void show_trace(struct task_struct *tsk, unsigned long *sp,
+ struct pt_regs *regs)
{
- unsigned long *stack, addr;
- unsigned long module_start = VMALLOC_START;
- unsigned long module_end = VMALLOC_END;
- int i = 1;
-
- if (!tsk)
- tsk = current;
- if (tsk == current)
- sp = (unsigned long *)current_stack_pointer;
- else
- sp = (unsigned long *)tsk->thread.sp;
+ unsigned long addr;
- stack = sp;
+ if (regs && user_mode(regs))
+ return;
printk("\nCall trace: ");
#ifdef CONFIG_KALLSYMS
printk("\n");
#endif
- while (!kstack_end(stack)) {
- addr = *stack++;
- if (((addr >= (unsigned long)_text) &&
- (addr <= (unsigned long)_etext)) ||
- ((addr >= module_start) && (addr <= module_end))) {
- /*
- * For 80-columns display, 6 entry is maximum.
- * NOTE: '[<8c00abcd>] ' consumes 13 columns .
- */
-#ifndef CONFIG_KALLSYMS
- if (i && ((i % 6) == 0))
- printk("\n ");
-#endif
- printk("[<%08lx>] ", addr);
- print_symbol("%s\n", addr);
- i++;
- }
+ while (!kstack_end(sp)) {
+ addr = *sp++;
+ if (kernel_text_address(addr))
+ print_ip_sym(addr);
}
printk("\n");
}
-void show_task(unsigned long *sp)
+void show_stack(struct task_struct *tsk, unsigned long *sp)
{
- show_stack(NULL, sp);
+ unsigned long stack;
+
+ if (!tsk)
+ tsk = current;
+ if (tsk == current)
+ sp = (unsigned long *)current_stack_pointer;
+ else
+ sp = (unsigned long *)tsk->thread.sp;
+
+ stack = (unsigned long)sp;
+ dump_mem("Stack: ", stack, THREAD_SIZE +
+ (unsigned long)task_stack_page(tsk));
+ show_trace(tsk, sp, NULL);
}
void dump_stack(void)
static void __exit amb_module_exit (void)
{
PRINTD (DBG_FLOW|DBG_INIT, "cleanup_module");
-
- return pci_unregister_driver(&amb_driver);
+
+ pci_unregister_driver(&amb_driver);
}
module_init(amb_module_init);
r = ROUND_UP;
}
error = make_rate (pcr, r, &tmc0, NULL);
+ if (error) {
+ kfree(tc);
+ return error;
+ }
}
fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
}
static void __exit hrz_module_exit (void) {
PRINTD (DBG_FLOW, "cleanup_module");
-
- return pci_unregister_driver(&hrz_driver);
+
+ pci_unregister_driver(&hrz_driver);
}
module_init(hrz_module_init);
{
ns_dev *card;
pool_levels pl;
- int btype;
+ long btype;
unsigned long flags;
card = dev->dev_data;
case NS_ADJBUFLEV:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
- btype = (int) arg; /* an int is the same size as a pointer */
+ btype = (long) arg; /* a long is the same size as a pointer or bigger */
switch (btype)
{
case NS_BUFTYPE_SMALL:
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/adc.h>
-#include <asm/hp6xx/hp6xx.h>
+#include <asm/hp6xx.h>
#define MODNAME "hp680_ts_input"
* is marked here since the boot video device will be the only enabled
* video device at this point.
*/
-
+#if 0
static void __devinit fixup_video(struct pci_dev *pdev)
{
struct pci_dev *bridge;
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_video);
-
+#endif
static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
{
#include <asm/io.h>
#include <asm/hd64461.h>
#include <asm/cpu/dac.h>
-#include <asm/hp6xx/hp6xx.h>
#define WIDTH 640
struct inomap *imap;
int block_offset;
int inodes_left;
- uint pageno;
+ unsigned long pageno;
int rel_inode;
jfs_info("diRead: ino = %ld", ip->i_ino);
int block_offset;
int inodes_left;
struct metapage *mp;
- uint pageno;
+ unsigned long pageno;
int rel_inode;
int dioffset;
struct inode *ipimap;
--- /dev/null
+/*
+ * include/asm-sh/edosk7705/io.h
+ *
+ * Modified version of io_se.h for the EDOSK7705 specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License. See linux/COPYING for more information.
+ *
+ * IO functions for an Hitachi EDOSK7705 development board
+ */
+
+#ifndef __ASM_SH_EDOSK7705_IO_H
+#define __ASM_SH_EDOSK7705_IO_H
+
+#include <asm/io_generic.h>
+
+extern unsigned char sh_edosk7705_inb(unsigned long port);
+extern unsigned int sh_edosk7705_inl(unsigned long port);
+
+extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
+extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
+
+extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
+extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
+
+extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
+
+#endif /* __ASM_SH_EDOSK7705_IO_H */
+++ /dev/null
-/*
- * include/asm-sh/edosk7705/io.h
- *
- * Modified version of io_se.h for the EDOSK7705 specific functions.
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * IO functions for an Hitachi EDOSK7705 development board
- */
-
-#ifndef __ASM_SH_EDOSK7705_IO_H
-#define __ASM_SH_EDOSK7705_IO_H
-
-#include <asm/io_generic.h>
-
-extern unsigned char sh_edosk7705_inb(unsigned long port);
-extern unsigned int sh_edosk7705_inl(unsigned long port);
-
-extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
-extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
-
-extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
-extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
-extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
-extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
-
-#endif /* __ASM_SH_EDOSK7705_IO_H */
--- /dev/null
+#ifndef __ASM_SH_HP6XX_H
+#define __ASM_SH_HP6XX_H
+
+/*
+ * Copyright (C) 2003, 2004, 2005 Andriy Skulysh
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define HP680_BTN_IRQ IRQ0_IRQ
+#define HP680_TS_IRQ IRQ3_IRQ
+#define HP680_HD64461_IRQ IRQ4_IRQ
+
+#define DAC_LCD_BRIGHTNESS 0
+#define DAC_SPEAKER_VOLUME 1
+
+#define PGDR_OPENED 0x01
+#define PGDR_MAIN_BATTERY_OUT 0x04
+#define PGDR_PLAY_BUTTON 0x08
+#define PGDR_REWIND_BUTTON 0x10
+#define PGDR_RECORD_BUTTON 0x20
+
+#define PHDR_TS_PEN_DOWN 0x08
+
+#define PJDR_LED_BLINK 0x02
+
+#define PKDR_LED_GREEN 0x10
+
+#define SCPDR_TS_SCAN_ENABLE 0x20
+#define SCPDR_TS_SCAN_Y 0x02
+#define SCPDR_TS_SCAN_X 0x01
+
+#define SCPCR_TS_ENABLE 0x405
+#define SCPCR_TS_MASK 0xc0f
+
+#define ADC_CHANNEL_TS_Y 1
+#define ADC_CHANNEL_TS_X 2
+#define ADC_CHANNEL_BATTERY 3
+#define ADC_CHANNEL_BACKUP 4
+#define ADC_CHANNEL_CHARGE 5
+
+#define HD64461_GPADR_SPEAKER 0x01
+#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
+
+#define HD64461_GPBDR_LCDOFF 0x01
+#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
+#define HD64461_GPBDR_LED_RED 0x80
+
+#include <asm/hd64461.h>
+#include <asm/io.h>
+
+#define PJDR 0xa4000130
+#define PKDR 0xa4000132
+
+static inline void hp6xx_led_red(int on)
+{
+ u16 v16;
+ v16 = ctrl_inw(CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
+ if (on)
+ ctrl_outw(v16 & (~HD64461_GPBDR_LED_RED), CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
+ else
+ ctrl_outw(v16 | HD64461_GPBDR_LED_RED, CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
+}
+
+static inline void hp6xx_led_green(int on)
+{
+ u8 v8;
+
+ v8 = ctrl_inb(PKDR);
+ if (on)
+ ctrl_outb(v8 & (~PKDR_LED_GREEN), PKDR);
+ else
+ ctrl_outb(v8 | PKDR_LED_GREEN, PKDR);
+}
+
+
+#endif /* __ASM_SH_HP6XX_H */
+++ /dev/null
-#ifndef __ASM_SH_HP6XX_H
-#define __ASM_SH_HP6XX_H
-
-/*
- * Copyright (C) 2003, 2004, 2005 Andriy Skulysh
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-
-#define HP680_BTN_IRQ IRQ0_IRQ
-#define HP680_TS_IRQ IRQ3_IRQ
-#define HP680_HD64461_IRQ IRQ4_IRQ
-
-#define DAC_LCD_BRIGHTNESS 0
-#define DAC_SPEAKER_VOLUME 1
-
-#define PGDR_OPENED 0x01
-#define PGDR_MAIN_BATTERY_OUT 0x04
-#define PGDR_PLAY_BUTTON 0x08
-#define PGDR_REWIND_BUTTON 0x10
-#define PGDR_RECORD_BUTTON 0x20
-
-#define PHDR_TS_PEN_DOWN 0x08
-
-#define PJDR_LED_BLINK 0x02
-
-#define PKDR_LED_GREEN 0x10
-
-#define SCPDR_TS_SCAN_ENABLE 0x20
-#define SCPDR_TS_SCAN_Y 0x02
-#define SCPDR_TS_SCAN_X 0x01
-
-#define SCPCR_TS_ENABLE 0x405
-#define SCPCR_TS_MASK 0xc0f
-
-#define ADC_CHANNEL_TS_Y 1
-#define ADC_CHANNEL_TS_X 2
-#define ADC_CHANNEL_BATTERY 3
-#define ADC_CHANNEL_BACKUP 4
-#define ADC_CHANNEL_CHARGE 5
-
-#define HD64461_GPADR_SPEAKER 0x01
-#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
-
-#define HD64461_GPBDR_LCDOFF 0x01
-#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
-#define HD64461_GPBDR_LED_RED 0x80
-
-#include <asm/hd64461.h>
-#include <asm/io.h>
-
-#define PJDR 0xa4000130
-#define PKDR 0xa4000132
-
-static inline void hp6xx_led_red(int on)
-{
- u16 v16;
- v16 = ctrl_inw(CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
- if (on)
- ctrl_outw(v16 & (~HD64461_GPBDR_LED_RED), CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
- else
- ctrl_outw(v16 | HD64461_GPBDR_LED_RED, CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
-}
-
-static inline void hp6xx_led_green(int on)
-{
- u8 v8;
-
- v8 = ctrl_inb(PKDR);
- if (on)
- ctrl_outb(v8 & (~PKDR_LED_GREEN), PKDR);
- else
- ctrl_outb(v8 | PKDR_LED_GREEN, PKDR);
-}
-
-
-#endif /* __ASM_SH_HP6XX_H */
+++ /dev/null
-#ifndef __ASM_SH_HP6XX_IDE_H
-#define __ASM_SH_HP6XX_IDE_H
-
-#define IRQ_CFCARD 93
-#define IRQ_PCMCIA 94
-
-#endif /* __ASM_SH_HP6XX_IDE_H */
-
+++ /dev/null
-#ifndef __ASM_SH_HP6XX_IO_H
-#define __ASM_SH_HP6XX_IO_H
-
-/*
- * Nothing special here.. just use the generic cchip io routines.
- */
-#include <asm/hd64461.h>
-
-#endif /* __ASM_SH_HP6XX_IO_H */
-
--- /dev/null
+#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H
+#define __ASM_SH_RENESAS_HS7751RVOIP_H
+
+/*
+ * linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h
+ *
+ * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Technology Sales HS7751RVoIP support
+ */
+
+/* Box specific addresses. */
+
+#define PA_BCR 0xa4000000 /* FPGA */
+#define PA_SLICCNTR1 0xa4000006 /* SLIC PIO Control 1 */
+#define PA_SLICCNTR2 0xa4000008 /* SLIC PIO Control 2 */
+#define PA_DMACNTR 0xa400000a /* USB DMA Control */
+#define PA_INPORTR 0xa400000c /* Input Port Register */
+#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
+#define PA_VERREG 0xa4000014 /* FPGA Version Register */
+
+#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
+
+#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
+#define IRLCNTR2 (PA_BCR + 2) /* Interrupt Control Register2 */
+#define IRLCNTR3 (PA_BCR + 4) /* Interrupt Control Register3 */
+#define IRLCNTR4 (PA_BCR + 16) /* Interrupt Control Register4 */
+#define IRLCNTR5 (PA_BCR + 18) /* Interrupt Control Register5 */
+
+#define IRQ_PCIETH 6 /* PCI Ethernet IRQ */
+#define IRQ_PCIHUB 7 /* PCI Ethernet Hub IRQ */
+#define IRQ_USBCOM 8 /* USB Comunication IRQ */
+#define IRQ_USBCON 9 /* USB Connect IRQ */
+#define IRQ_USBDMA 10 /* USB DMA IRQ */
+#define IRQ_CFCARD 11 /* CF Card IRQ */
+#define IRQ_PCMCIA 12 /* PCMCIA IRQ */
+#define IRQ_PCISLOT 13 /* PCI Slot #1 IRQ */
+#define IRQ_ONHOOK1 0 /* ON HOOK1 IRQ */
+#define IRQ_OFFHOOK1 1 /* OFF HOOK1 IRQ */
+#define IRQ_ONHOOK2 2 /* ON HOOK2 IRQ */
+#define IRQ_OFFHOOK2 3 /* OFF HOOK2 IRQ */
+#define IRQ_RINGING 4 /* Ringing IRQ */
+#define IRQ_CODEC 5 /* CODEC IRQ */
+
+#define __IO_PREFIX hs7751rvoip
+#include <asm/io_generic.h>
+
+/* arch/sh/boards/renesas/hs7751rvoip/irq.c */
+void init_hs7751rvoip_IRQ(void);
+
+/* arch/sh/boards/renesas/hs7751rvoip/io.c */
+void *hs7751rvoip_ioremap(unsigned long, unsigned long);
+
+#endif /* __ASM_SH_RENESAS_HS7751RVOIP */
+++ /dev/null
-#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H
-#define __ASM_SH_RENESAS_HS7751RVOIP_H
-
-/*
- * linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h
- *
- * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
- *
- * Renesas Technology Sales HS7751RVoIP support
- */
-
-/* Box specific addresses. */
-
-#define PA_BCR 0xa4000000 /* FPGA */
-#define PA_SLICCNTR1 0xa4000006 /* SLIC PIO Control 1 */
-#define PA_SLICCNTR2 0xa4000008 /* SLIC PIO Control 2 */
-#define PA_DMACNTR 0xa400000a /* USB DMA Control */
-#define PA_INPORTR 0xa400000c /* Input Port Register */
-#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
-#define PA_VERREG 0xa4000014 /* FPGA Version Register */
-
-#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
-
-#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
-#define IRLCNTR2 (PA_BCR + 2) /* Interrupt Control Register2 */
-#define IRLCNTR3 (PA_BCR + 4) /* Interrupt Control Register3 */
-#define IRLCNTR4 (PA_BCR + 16) /* Interrupt Control Register4 */
-#define IRLCNTR5 (PA_BCR + 18) /* Interrupt Control Register5 */
-
-#define IRQ_PCIETH 6 /* PCI Ethernet IRQ */
-#define IRQ_PCIHUB 7 /* PCI Ethernet Hub IRQ */
-#define IRQ_USBCOM 8 /* USB Comunication IRQ */
-#define IRQ_USBCON 9 /* USB Connect IRQ */
-#define IRQ_USBDMA 10 /* USB DMA IRQ */
-#define IRQ_CFCARD 11 /* CF Card IRQ */
-#define IRQ_PCMCIA 12 /* PCMCIA IRQ */
-#define IRQ_PCISLOT 13 /* PCI Slot #1 IRQ */
-#define IRQ_ONHOOK1 0 /* ON HOOK1 IRQ */
-#define IRQ_OFFHOOK1 1 /* OFF HOOK1 IRQ */
-#define IRQ_ONHOOK2 2 /* ON HOOK2 IRQ */
-#define IRQ_OFFHOOK2 3 /* OFF HOOK2 IRQ */
-#define IRQ_RINGING 4 /* Ringing IRQ */
-#define IRQ_CODEC 5 /* CODEC IRQ */
-
-#define __IO_PREFIX hs7751rvoip
-#include <asm/io_generic.h>
-
-/* arch/sh/boards/renesas/hs7751rvoip/irq.c */
-void init_hs7751rvoip_IRQ(void);
-
-/* arch/sh/boards/renesas/hs7751rvoip/io.c */
-void *hs7751rvoip_ioremap(unsigned long, unsigned long);
-
-#endif /* __ASM_SH_RENESAS_HS7751RVOIP */
+++ /dev/null
-#ifndef __ASM_SH_HS7751RVOIP_IDE_H
-#define __ASM_SH_HS7751RVOIP_IDE_H
-
-/* Nothing to see here.. */
-#include <asm/hs7751rvoip/hs7751rvoip.h>
-
-#endif /* __ASM_SH_HS7751RVOIP_IDE_H */
-
*
* Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
*/
-
-#ifdef CONFIG_IDE
-# ifndef IRQ_CFCARD
-# define IRQ_CFCARD 14
-# endif
-# ifndef IRQ_PCMCIA
-# define IRQ_PCMCIA 15
-# endif
-#endif
-
#define INTC_BASE 0xffd00000
#define INTC_ICR0 (INTC_BASE+0x0)
#define INTC_ICR1 (INTC_BASE+0x1c)
#include <asm/machvec.h>
#include <asm/ptrace.h> /* for pt_regs */
-#if defined(CONFIG_SH_HP6XX) || \
- defined(CONFIG_SH_RTS7751R2D) || \
- defined(CONFIG_SH_HS7751RVOIP) || \
- defined(CONFIG_SH_HS7751RVOIP) || \
- defined(CONFIG_SH_SH03) || \
- defined(CONFIG_SH_R7780RP) || \
- defined(CONFIG_SH_LANDISK)
-#include <asm/mach/ide.h>
-#endif
-
#ifndef CONFIG_CPU_SUBTYPE_SH7780
#define INTC_DMAC0_MSK 0
#define INTC_IPRD 0xffd00010UL
#endif
-#ifdef CONFIG_IDE
-# ifndef IRQ_CFCARD
-# define IRQ_CFCARD 14
-# endif
-# ifndef IRQ_PCMCIA
-# define IRQ_PCMCIA 15
-# endif
-#endif
-
#define TIMER_IRQ 16
#define TIMER_IPR_ADDR INTC_IPRA
#define TIMER_IPR_POS 3
unsigned char priority;
};
-void make_intc2_irq(struct intc2_data *);
+void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
void init_IRQ_intc2(void);
#endif
+++ /dev/null
-/*
- * modifed by kogiidena
- * 2005.03.03
- */
-
-#ifndef __ASM_SH_LANDISK_IDE_H
-#define __ASM_SH_LANDISK_IDE_H
-
-/* Nothing to see here.. */
-#include <asm/landisk/iodata_landisk.h>
-#define IRQ_CFCARD IRQ_FATA /* CF Card IRQ */
-#define IRQ_PCMCIA IRQ_ATA /* PCMCIA IRQ */
-
-#endif /* __ASM_SH_LANDISK_IDE_H */
*/
#define thread_saved_pc(tsk) (tsk->thread.pc)
+void show_trace(struct task_struct *tsk, unsigned long *sp,
+ struct pt_regs *regs);
extern unsigned long get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) ((tsk)->thread.pc)
--- /dev/null
+#ifndef __ASM_SH_RENESAS_R7780RP_H
+#define __ASM_SH_RENESAS_R7780RP_H
+
+/*
+ * linux/include/asm-sh/r7780rp.h
+ *
+ * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Solutions Highlander R7780RP support
+ */
+
+/* Box specific addresses. */
+#if defined(CONFIG_SH_R7780MP)
+#define PA_BCR 0xa4000000 /* FPGA */
+#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
+#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
+#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
+#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
+#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
+#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
+#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
+#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
+#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
+#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
+#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
+#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
+#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
+#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
+#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
+#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
+#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
+#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
+#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
+#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
+#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
+#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
+#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
+#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
+#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
+#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
+#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
+#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
+#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
+#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
+#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
+#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
+#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
+#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
+#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
+#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
+#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
+#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
+#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
+#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
+#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
+#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
+#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
+#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
+#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
+#define PA_PMR (PA_BCR+0x0900) /* */
+
+#define PA_AX88796L 0xa4100400 /* AX88796L Area */
+#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
+#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
+#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
+
+#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
+
+#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
+#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
+#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
+#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
+// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
+#define IRQ_TP 2 /* Touch Panel IRQ */
+#define IRQ_SCI1 3 /* SCI1 IRQ */
+#define IRQ_SCI0 4 /* SCI0 IRQ */
+#define IRQ_2SERIAL 5 /* Serial IRQ */
+#define IRQ_RTC 6 /* RTC A / B IRQ */
+#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
+#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
+#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
+#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
+#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
+#define IRQ_ONETH 13 /* On board Ethernet IRQ */
+#define IRQ_PSW 14 /* Push Switch IRQ */
+
+#else /* R7780RP */
+
+#define PA_BCR 0xa5000000 /* FPGA */
+#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
+#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
+#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
+#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
+#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
+#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
+#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
+#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
+#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
+#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
+#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
+#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
+#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
+#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
+#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
+#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
+#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
+#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
+#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
+#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
+#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
+#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
+#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
+#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
+#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
+#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
+#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
+#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
+#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
+#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
+#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
+
+#define PA_AX88796L 0xa5800400 /* AX88796L Area */
+#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
+#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
+#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
+
+#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
+
+#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
+#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
+#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
+#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
+#define IRQ_CFINST 5 /* CF Card Insert IRQ */
+#define IRQ_M66596 6 /* M66596 IRQ */
+#define IRQ_SDCARD 7 /* SD Card IRQ */
+#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
+#define IRQ_SCI 9 /* SCI IRQ */
+#define IRQ_2SERIAL 10 /* Serial IRQ */
+#define IRQ_EXTENTION 11 /* EXTn IRQ */
+#define IRQ_ONETH 12 /* On board Ethernet IRQ */
+#define IRQ_PSW 13 /* Push Switch IRQ */
+#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
+
+#endif /* CONFIG_SH_R7780MP */
+
+#define __IO_PREFIX r7780rp
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_RENESAS_R7780RP */
+++ /dev/null
-#ifndef __ASM_SH_R7780RP_IDE_H
-#define __ASM_SH_R7780RP_IDE_H
-
-/* Nothing to see here.. */
-#include <asm/mach/r7780rp.h>
-
-#endif /* __ASM_SH_R7780RP_IDE_H */
-
+++ /dev/null
-#ifndef __ASM_SH_RENESAS_R7780RP_H
-#define __ASM_SH_RENESAS_R7780RP_H
-
-/*
- * linux/include/asm-sh/r7780rp.h
- *
- * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
- *
- * Renesas Solutions Highlander R7780RP support
- */
-
-/* Box specific addresses. */
-#if defined(CONFIG_SH_R7780MP)
-#define PA_BCR 0xa4000000 /* FPGA */
-#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
-#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
-#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
-#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
-#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
-#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
-#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
-#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
-#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
-#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
-#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
-#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
-#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
-#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
-#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
-#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
-#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
-#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
-#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
-#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
-#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
-#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
-#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
-#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
-#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
-#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
-#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
-#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
-#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
-#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
-#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
-#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
-#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
-#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
-#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
-#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
-#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
-#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
-#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
-#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
-#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
-#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
-#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
-#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
-#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
-#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
-#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
-#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
-#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
-#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
-#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
-#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
-#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
-#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
-#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
-#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
-#define PA_PMR (PA_BCR+0x0900) /* */
-
-#define PA_AX88796L 0xa4100400 /* AX88796L Area */
-#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
-#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
-#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
-#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
-#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
-
-#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
-
-#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
-#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
-#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
-#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
-#define IRQ_CFCARD 1 /* CF Card IRQ */
-// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
-#define IRQ_TP 2 /* Touch Panel IRQ */
-#define IRQ_SCI1 3 /* SCI1 IRQ */
-#define IRQ_SCI0 4 /* SCI0 IRQ */
-#define IRQ_2SERIAL 5 /* Serial IRQ */
-#define IRQ_RTC 6 /* RTC A / B IRQ */
-#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
-#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
-#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
-#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
-#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
-#define IRQ_ONETH 13 /* On board Ethernet IRQ */
-#define IRQ_PSW 14 /* Push Switch IRQ */
-
-#else /* R7780RP */
-
-#define PA_BCR 0xa5000000 /* FPGA */
-#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
-#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
-#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
-#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
-#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
-#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
-#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
-#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
-#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
-#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
-#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
-#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
-#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
-#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
-#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
-#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
-#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
-#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
-#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
-#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
-#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
-#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
-#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
-#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
-#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
-#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
-#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
-#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
-#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
-#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
-#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
-#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
-#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
-#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
-#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
-#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
-#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
-#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
-#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
-#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
-#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
-#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
-
-#define PA_AX88796L 0xa5800400 /* AX88796L Area */
-#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
-#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
-#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
-#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
-#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
-
-#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
-
-#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
-#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
-#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
-#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
-#define IRQ_CFCARD 4 /* CF Card IRQ */
-#define IRQ_CFINST 5 /* CF Card Insert IRQ */
-#define IRQ_M66596 6 /* M66596 IRQ */
-#define IRQ_SDCARD 7 /* SD Card IRQ */
-#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
-#define IRQ_SCI 9 /* SCI IRQ */
-#define IRQ_2SERIAL 10 /* Serial IRQ */
-#define IRQ_EXTENTION 11 /* EXTn IRQ */
-#define IRQ_ONETH 12 /* On board Ethernet IRQ */
-#define IRQ_PSW 13 /* Push Switch IRQ */
-#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
-
-#endif /* CONFIG_SH_R7780MP */
-
-#define __IO_PREFIX r7780rp
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_RENESAS_R7780RP */
--- /dev/null
+#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
+#define __ASM_SH_RENESAS_RTS7751R2D_H
+
+/*
+ * linux/include/asm-sh/renesas_rts7751r2d.h
+ *
+ * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Technology Sales RTS7751R2D support
+ */
+
+/* Box specific addresses. */
+
+#define PA_BCR 0xa4000000 /* FPGA */
+#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
+#define PA_CFCTL 0xa4000004 /* CF Timing control */
+#define PA_CFPOW 0xa4000006 /* CF Power control */
+#define PA_DISPCTL 0xa4000008 /* Display Timing control */
+#define PA_SDMPOW 0xa400000a /* SD Power control */
+#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
+#define PA_PCICD 0xa400000e /* PCI Extention detect control */
+#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
+#if defined(CONFIG_RTS7751R2D_REV11)
+#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */
+#define PA_CFRST 0xa4000024 /* CF Reset control */
+#define PA_ADMRTS 0xa4000026 /* SD Reset control */
+#define PA_EXTRST 0xa4000028 /* Extention Reset control */
+#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
+#else
+#define PA_CFRST 0xa4000022 /* CF Reset control */
+#define PA_ADMRTS 0xa4000024 /* SD Reset control */
+#define PA_EXTRST 0xa4000026 /* Extention Reset control */
+#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
+#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
+#endif
+#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
+#define PA_VERREG 0xa4000032 /* FPGA Version Register */
+#define PA_INPORT 0xa4000034 /* KEY Input Port control */
+#define PA_OUTPORT 0xa4000036 /* LED control */
+#define PA_DMPORT 0xa4000038 /* DM270 Output Port control */
+
+#define PA_AX88796L 0xaa000400 /* AX88796L Area */
+#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
+#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
+#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
+
+#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
+
+#if defined(CONFIG_RTS7751R2D_REV11)
+#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */
+#define IRQ_CFCARD 1 /* CF Card IRQ */
+#define IRQ_CFINST 2 /* CF Card Insert IRQ */
+#define IRQ_PCMCIA 3 /* PCMCIA IRQ */
+#define IRQ_VOYAGER 4 /* VOYAGER IRQ */
+#define IRQ_ONETH 5 /* On board Ethernet IRQ */
+#else
+#define IRQ_KEYIN 0 /* Key Input IRQ */
+#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */
+#define IRQ_CFCARD 2 /* CF Card IRQ */
+#define IRQ_CFINST 3 /* CF Card Insert IRQ */
+#define IRQ_PCMCIA 4 /* PCMCIA IRQ */
+#define IRQ_VOYAGER 5 /* VOYAGER IRQ */
+#endif
+#define IRQ_RTCALM 6 /* RTC Alarm IRQ */
+#define IRQ_RTCTIME 7 /* RTC Timer IRQ */
+#define IRQ_SDCARD 8 /* SD Card IRQ */
+#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */
+#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */
+#define IRQ_EXTENTION 11 /* EXTn IRQ */
+
+#define __IO_PREFIX rts7751r2d
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_RENESAS_RTS7751R2D */
+++ /dev/null
-#ifndef __ASM_SH_RTS7751R2D_IDE_H
-#define __ASM_SH_RTS7751R2D_IDE_H
-
-/* Nothing to see here.. */
-#include <asm/rts7751r2d/rts7751r2d.h>
-
-#endif /* __ASM_SH_RTS7751R2D_IDE_H */
-
+++ /dev/null
-#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
-#define __ASM_SH_RENESAS_RTS7751R2D_H
-
-/*
- * linux/include/asm-sh/renesas_rts7751r2d.h
- *
- * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
- *
- * Renesas Technology Sales RTS7751R2D support
- */
-
-/* Box specific addresses. */
-
-#define PA_BCR 0xa4000000 /* FPGA */
-#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
-#define PA_CFCTL 0xa4000004 /* CF Timing control */
-#define PA_CFPOW 0xa4000006 /* CF Power control */
-#define PA_DISPCTL 0xa4000008 /* Display Timing control */
-#define PA_SDMPOW 0xa400000a /* SD Power control */
-#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
-#define PA_PCICD 0xa400000e /* PCI Extention detect control */
-#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
-#if defined(CONFIG_RTS7751R2D_REV11)
-#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */
-#define PA_CFRST 0xa4000024 /* CF Reset control */
-#define PA_ADMRTS 0xa4000026 /* SD Reset control */
-#define PA_EXTRST 0xa4000028 /* Extention Reset control */
-#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
-#else
-#define PA_CFRST 0xa4000022 /* CF Reset control */
-#define PA_ADMRTS 0xa4000024 /* SD Reset control */
-#define PA_EXTRST 0xa4000026 /* Extention Reset control */
-#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
-#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
-#endif
-#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
-#define PA_VERREG 0xa4000032 /* FPGA Version Register */
-#define PA_INPORT 0xa4000034 /* KEY Input Port control */
-#define PA_OUTPORT 0xa4000036 /* LED control */
-#define PA_DMPORT 0xa4000038 /* DM270 Output Port control */
-
-#define PA_AX88796L 0xaa000400 /* AX88796L Area */
-#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
-#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
-#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
-
-#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
-
-#if defined(CONFIG_RTS7751R2D_REV11)
-#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */
-#define IRQ_CFCARD 1 /* CF Card IRQ */
-#define IRQ_CFINST 2 /* CF Card Insert IRQ */
-#define IRQ_PCMCIA 3 /* PCMCIA IRQ */
-#define IRQ_VOYAGER 4 /* VOYAGER IRQ */
-#define IRQ_ONETH 5 /* On board Ethernet IRQ */
-#else
-#define IRQ_KEYIN 0 /* Key Input IRQ */
-#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */
-#define IRQ_CFCARD 2 /* CF Card IRQ */
-#define IRQ_CFINST 3 /* CF Card Insert IRQ */
-#define IRQ_PCMCIA 4 /* PCMCIA IRQ */
-#define IRQ_VOYAGER 5 /* VOYAGER IRQ */
-#endif
-#define IRQ_RTCALM 6 /* RTC Alarm IRQ */
-#define IRQ_RTCTIME 7 /* RTC Timer IRQ */
-#define IRQ_SDCARD 8 /* SD Card IRQ */
-#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */
-#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */
-#define IRQ_EXTENTION 11 /* EXTn IRQ */
-
-#define __IO_PREFIX rts7751r2d
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_RENESAS_RTS7751R2D */
+++ /dev/null
-#ifndef __ASM_SH_SH03_IDE_H
-#define __ASM_SH_SH03_IDE_H
-
-#define IRQ_CFCARD 8
-#define IRQ_PCMCIA 8
-
-#endif /* __ASM_SH_SH03_IDE_H */
--- /dev/null
+#ifndef __ASM_SH_SHMIN_H
+#define __ASM_SH_SHMIN_H
+
+#define SHMIN_IO_BASE 0xb0000000UL
+
+#define SHMIN_NE_IRQ IRQ2_IRQ
+#define SHMIN_NE_BASE 0x300
+
+#endif
+++ /dev/null
-#ifndef __ASM_SH_SHMIN_H
-#define __ASM_SH_SHMIN_H
-
-#define SHMIN_IO_BASE 0xb0000000UL
-
-#define SHMIN_NE_IRQ IRQ2_IRQ
-#define SHMIN_NE_BASE 0x300
-
-#endif
(unsigned long)_n_, sizeof(*(ptr))); \
})
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+ return set_exception_table_vec(evt >> 5, handler);
+}
+
/* XXX
* disable hlt during certain critical i/o operations
*/
return (u32)(unsigned long)uptr;
}
-static __inline__ void __user *compat_alloc_user_space(long len)
+static inline void __user *compat_alloc_user_space(long len)
{
struct pt_regs *regs = current_thread_info()->kregs;
unsigned long usp = regs->u_regs[UREG_I6];
else
usp &= 0xffffffffUL;
- return (void __user *) (usp - len);
+ usp -= len;
+ usp &= ~0x7UL;
+
+ return (void __user *) usp;
}
struct compat_ipc64_perm {
{
fl->uli_u.dnports.sport = scp->addrloc;
fl->uli_u.dnports.dport = scp->addrrem;
- fl->uli_u.dnports.objnum = scp->addr.sdn_objnum;
- if (fl->uli_u.dnports.objnum == 0) {
- fl->uli_u.dnports.objnamel = (__u8)dn_ntohs(scp->addr.sdn_objnamel);
- memcpy(fl->uli_u.dnports.objname, scp->addr.sdn_objname, 16);
- }
}
extern unsigned dn_mss_from_pmtu(struct net_device *dev, int mtu);
struct {
__le16 sport;
__le16 dport;
- __u8 objnum;
- __u8 objnamel; /* Not 16 bits since max val is 16 */
- __u8 objname[16]; /* Not zero terminated */
} dnports;
__be32 spi;
/**
* sk_filter_release: Release a socket filter
- * @sk: socket
- * @fp: filter to remove
+ * @rcu: rcu_head that contains the sk_filter info to remove
*
* Remove a filter from a socket and release its resources.
*/
int atm_register_sysfs(struct atm_dev *adev)
{
struct class_device *cdev = &adev->class_dev;
- int i, err;
+ int i, j, err;
cdev->class = &atm_class;
class_set_devdata(cdev, adev);
if (err < 0)
return err;
- for (i = 0; atm_attrs[i]; i++)
- class_device_create_file(cdev, atm_attrs[i]);
+ for (i = 0; atm_attrs[i]; i++) {
+ err = class_device_create_file(cdev, atm_attrs[i]);
+ if (err)
+ goto err_out;
+ }
return 0;
+
+err_out:
+ for (j = 0; j < i; j++)
+ class_device_remove_file(cdev, atm_attrs[j]);
+ class_device_del(cdev);
+ return err;
}
void atm_unregister_sysfs(struct atm_dev *adev)
dccp_hdr(skb)->dccph_sport);
}
+static struct request_sock_ops dccp_request_sock_ops;
+
int dccp_v4_conn_request(struct sock *sk, struct sk_buff *skb)
{
struct inet_request_sock *ireq;
if (sk_acceptq_is_full(sk) && inet_csk_reqsk_queue_young(sk) > 1)
goto drop;
- req = reqsk_alloc(sk->sk_prot->rsk_prot);
+ req = reqsk_alloc(&dccp_request_sock_ops);
if (req == NULL)
goto drop;
static int dccp_v6_conn_request(struct sock *sk, struct sk_buff *skb)
{
- struct inet_request_sock *ireq;
struct dccp_sock dp;
struct request_sock *req;
struct dccp_request_sock *dreq;
if (sk_acceptq_is_full(sk) && inet_csk_reqsk_queue_young(sk) > 1)
goto drop;
- req = inet6_reqsk_alloc(sk->sk_prot->rsk_prot);
+ req = inet6_reqsk_alloc(&dccp6_request_sock_ops);
if (req == NULL)
goto drop;
goto drop_and_free;
ireq6 = inet6_rsk(req);
- ireq = inet_rsk(req);
ipv6_addr_copy(&ireq6->rmt_addr, &skb->nh.ipv6h->saddr);
ipv6_addr_copy(&ireq6->loc_addr, &skb->nh.ipv6h->daddr);
req->rcv_wnd = dccp_feat_default_sequence_window;
if (sk->sk_state == DCCP_OPEN) { /* Fast path */
if (dccp_rcv_established(sk, skb, dccp_hdr(skb), skb->len))
goto reset;
+ if (opt_skb) {
+ /* This is where we would goto ipv6_pktoptions. */
+ __kfree_skb(opt_skb);
+ }
return 0;
}
if (dccp_rcv_state_process(sk, skb, dccp_hdr(skb), skb->len))
goto reset;
+ if (opt_skb) {
+ /* This is where we would goto ipv6_pktoptions. */
+ __kfree_skb(opt_skb);
+ }
return 0;
reset:
static struct fib6_table fib6_main_tbl = {
.tb6_id = RT6_TABLE_MAIN,
- .tb6_lock = RW_LOCK_UNLOCKED,
.tb6_root = {
.leaf = &ip6_null_entry,
.fn_flags = RTN_ROOT | RTN_TL_ROOT | RTN_RTINFO,
{
unsigned int h;
+ /*
+ * Initialize table lock at a single place to give lockdep a key,
+ * tables aren't visible prior to being linked to the list.
+ */
+ rwlock_init(&tb->tb6_lock);
+
h = tb->tb6_id & (FIB_TABLE_HASHSZ - 1);
/*
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
static struct fib6_table fib6_local_tbl = {
.tb6_id = RT6_TABLE_LOCAL,
- .tb6_lock = RW_LOCK_UNLOCKED,
.tb6_root = {
.leaf = &ip6_null_entry,
.fn_flags = RTN_ROOT | RTN_TL_ROOT | RTN_RTINFO,
table = kzalloc(sizeof(*table), GFP_ATOMIC);
if (table != NULL) {
table->tb6_id = id;
- table->tb6_lock = RW_LOCK_UNLOCKED;
table->tb6_root.leaf = &ip6_null_entry;
table->tb6_root.fn_flags = RTN_ROOT | RTN_TL_ROOT | RTN_RTINFO;
}
return NET_XMIT_BYPASS;
}
+ skb_orphan(skb);
+
/*
* If we need to duplicate packet, then re-insert at top of the
* qdisc tree, since parent queuer expects that only one
#include <asm/cpu/dac.h>
#include <asm/cpu/timer.h>
#include <asm/machvec.h>
-#include <asm/hp6xx/hp6xx.h>
+#include <asm/hp6xx.h>
#include <asm/hd64461.h>
#define MODNAME "sh_dac_audio"
projects / firefly-linux-kernel-4.4.55.git / commitdiff