drm/rockchip: dsi: fix Non-SNPS PHY power on sequence

Change-Id: If9f131ec6ebc8b194034bf231ca2bcc120440860
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 9e2585372432d3a9359554b9188a946490aabad3..ffe4f0a52323bea70768ee503e88f7fee298301b 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -1112,6 +1112,13 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
                return;
        }
 
+       if (dsi->dphy.phy) {
+               rockchip_dsi_set_hs_clk(dsi);
+               phy_power_on(dsi->dphy.phy);
+       } else {
+               dw_mipi_dsi_get_lane_bps(dsi);
+       }
+
        pm_runtime_get_sync(dsi->dev);
 
        if (dsi->rst) {
@@ -1122,13 +1129,6 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
                udelay(10);
        }
 
-       if (dsi->dphy.phy) {
-               rockchip_dsi_set_hs_clk(dsi);
-               phy_power_on(dsi->dphy.phy);
-       } else {
-               dw_mipi_dsi_get_lane_bps(dsi);
-       }
-
        dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
                 dsi->lane_mbps, dsi->lanes);
 }