clk: rockchip: rk3399: move VOP clock to other PLLs

We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.

Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 73da861158d6576f9fb7512026c0791ed223ec1e..3e81113abf3283a6d7db4154463ac62e1931a7ed 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -139,8 +139,13 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)       = { "cpll", "gpll", "npll", "upll",
 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
 
 PNAME(mux_pll_src_vpll_cpll_gpll_p)            = { "vpll", "cpll", "gpll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)       = { "vpll", "cpll", "gpll", "npll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)                = { "vpll", "cpll", "gpll", "xin24m" };
+/*
+ * We hope to be able to HDMI/DP can obtain better signal quality,
+ * therefore, we move VOP pwm and aclk clocks to other PLLs, let
+ * HDMI/DP phyclock can monopolize VPLL.
+ */
+PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p)    = { "dummy_vpll", "cpll", "gpll", "npll" };
+PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)     = { "dummy_vpll", "cpll", "gpll", "xin24m" };
 
 PNAME(mux_dclk_vop0_p)                         = { "dclk_vop0_div", "dclk_vop0_frac" };
 PNAME(mux_dclk_vop1_p)                         = { "dclk_vop1_div", "dclk_vop1_frac" };
@@ -1113,7 +1118,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(11), 7, GFLAGS),
 
        /* vop0 */
-       COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
+       COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
                        RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 8, GFLAGS),
        COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
@@ -1138,12 +1143,12 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKSEL_CON(106), 0,
                        &rk3399_dclk_vop0_fracmux),
 
-       COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
+       COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
                        RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 14, GFLAGS),
 
        /* vop1 */
-       COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
+       COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
                        RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 10, GFLAGS),
        COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
@@ -1168,7 +1173,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKSEL_CON(107), 0,
                        &rk3399_dclk_vop1_fracmux),
 
-       COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
+       COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
                        RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 15, GFLAGS),