/*
* Setup the hardware configuration for a given hw_event_type
*/
-int hw_perf_counter_init(struct perf_counter *counter, s32 hw_event_type)
+int hw_perf_counter_init(struct perf_counter *counter)
{
struct hw_perf_counter *hwc = &counter->hw;
+ u32 hw_event_type = counter->event.hw_event_type;
if (unlikely(!perf_counters_initialized))
return -EINVAL;
hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0;
hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0;
- hwc->irq_period = counter->__irq_period;
+ hwc->irq_period = counter->event.hw_event_period;
/*
* Intel PMCs cannot be accessed sanely above 32 bit width,
* so we install an artificial 1<<31 period regardless of
hwc->next_count = -((s32) hwc->irq_period);
/*
- * Negative event types mean raw encoded event+umask values:
+ * Raw event type provide the config in the event structure
*/
- if (hw_event_type < 0) {
- counter->hw_event_type = -hw_event_type;
- counter->hw_event_type &= ~PERF_COUNT_NMI;
+ hw_event_type &= ~PERF_COUNT_NMI;
+ if (hw_event_type == PERF_COUNT_RAW) {
+ hwc->config |= counter->event.hw_raw_ctrl;
} else {
- hw_event_type &= ~PERF_COUNT_NMI;
if (hw_event_type >= max_intel_perfmon_events)
return -EINVAL;
/*
* The generic map:
*/
- counter->hw_event_type = intel_perfmon_event_map[hw_event_type];
+ hwc->config |= intel_perfmon_event_map[hw_event_type];
}
- hwc->config |= counter->hw_event_type;
counter->wakeup_pending = 0;
return 0;
perf_save_and_restart(counter);
}
}
- perf_store_irq_data(leader, counter->hw_event_type);
+ perf_store_irq_data(leader, counter->event.hw_event_type);
perf_store_irq_data(leader, atomic64_counter_read(counter));
}
}
perf_store_irq_data(counter, instruction_pointer(regs));
break;
case PERF_RECORD_GROUP:
- perf_store_irq_data(counter, counter->hw_event_type);
+ perf_store_irq_data(counter,
+ counter->event.hw_event_type);
perf_store_irq_data(counter,
atomic64_counter_read(counter));
perf_handle_group(counter, &status, &ack);
* Architecture provided APIs - weak aliases:
*/
-int __weak hw_perf_counter_init(struct perf_counter *counter, u32 hw_event_type)
+int __weak hw_perf_counter_init(struct perf_counter *counter)
{
return -EINVAL;
}
* Allocate and initialize a counter structure
*/
static struct perf_counter *
-perf_counter_alloc(u32 hw_event_period, int cpu, u32 record_type)
+perf_counter_alloc(struct perf_counter_event *event, int cpu, u32 record_type)
{
struct perf_counter *counter = kzalloc(sizeof(*counter), GFP_KERNEL);
counter->usrdata = &counter->data[1];
counter->cpu = cpu;
counter->record_type = record_type;
- counter->__irq_period = hw_event_period;
+ counter->event = *event;
counter->wakeup_pending = 0;
return counter;
return PTR_ERR(ctx);
ret = -ENOMEM;
- counter = perf_counter_alloc(event.hw_event_period, cpu, record_type);
+ counter = perf_counter_alloc(&event, cpu, record_type);
if (!counter)
goto err_put_context;
- ret = hw_perf_counter_init(counter, event.hw_event_type);
+ ret = hw_perf_counter_init(counter);
if (ret)
goto err_free_put_context;