Had expand logic backward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25105 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 9ce9a3ebe09d4c3c2905a215cc23bf46fee9316f..63a04e43b13362b927733dbc546442c0adca67b2 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -103,6 +103,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
 
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
   
   // We want to legalize GlobalAddress and ConstantPool and
   // ExternalSymbols nodes into the appropriate instructions to

diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index fb3b20476cd78bdcc37b9e80f839539b9605e3b1..31dba9293d8f4fbf86a4e6bfdcf3f1fb9941fc00 100644 (file)
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -74,6 +74,8 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
 
       // We don't have line number support yet.
       setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+      setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+      setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
 
       //IA64 has these, but they are not implemented
       setOperationAction(ISD::CTTZ , MVT::i64  , Expand);

diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 31e225913dc0f0e90f28b3f1a930bafc19056581..f1de338b2c0947e9079ff95b9e725e2ba993211f 100644 (file)
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -102,6 +102,8 @@ namespace {
 
       // We don't have line number support yet.
       setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+      setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+      setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
 
       computeRegisterProperties();
 

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 8eb4ac303a7d68ae465b9f57375d742d6fe459c2..9547b9e9d4f8bc4ad0a48c58204d212a1ca7f088 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -96,8 +96,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
 
   // Support label based line numbers.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
   // FIXME - use subtarget debug flags
-  if (TM.getSubtarget<PPCSubtarget>().isDarwin())
+  if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
     setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
   
   // We want to legalize GlobalAddress and ConstantPool nodes into the 

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index b80430dba5d027edf287c049228ab609ad2c7bce..d61c4f0c2f7d3d81a3d07cfab23c6675508d523f 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -153,6 +153,8 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
 
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
 
   computeRegisterProperties();
 }

diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index b80430dba5d027edf287c049228ab609ad2c7bce..d61c4f0c2f7d3d81a3d07cfab23c6675508d523f 100644 (file)
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -153,6 +153,8 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
 
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
 
   computeRegisterProperties();
 }

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 304165e4a80275df6f8ace86b371cebc81ed7231..c96049d440fa4fa9f3b1589f765b720a59b4b7bf 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -130,6 +130,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
 
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
 
   if (X86ScalarSSE) {
     // Set up the FP register classes.