Remove an unnecsesary file. PPC32 and PPC64 share architected registers.

We will decide with subtarget support whether we ever use an i64 register
class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23734 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC32.td b/lib/Target/PowerPC/PPC32.td
index e808e83b41a68ff6f45ed79c223631debc0004b4..42d130fe5e980b16de494e60cd6f7cfa99ecd8ed 100644 (file)
--- a/lib/Target/PowerPC/PPC32.td
+++ b/lib/Target/PowerPC/PPC32.td
@@ -18,7 +18,7 @@ include "../Target.td"
 // Register File Description
 //===----------------------------------------------------------------------===//
 
-include "PPC32RegisterInfo.td"
+include "PowerPCRegisterInfo.td"
 include "PowerPCInstrInfo.td"
 
 def PPC32 : Target {

diff --git a/lib/Target/PowerPC/PPC32RegisterInfo.td b/lib/Target/PowerPC/PPC32RegisterInfo.td
deleted file mode 100644 (file)
index ef2e623..0000000
--- a/lib/Target/PowerPC/PPC32RegisterInfo.td
+++ /dev/null
@@ -1,50 +0,0 @@
-//===- PPC32RegisterInfo.td - The PowerPC32 Register File --*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-include "PowerPCRegisterInfo.td"
-
-/// Register classes
-// Allocate volatiles first
-// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<"PPC32", i32, 32,
-     [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
-      R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
-      R16, R15, R14, R13, R31, R0, R1, LR]>
-{
-  let MethodProtos = [{
-    iterator allocation_order_begin(MachineFunction &MF) const;
-    iterator allocation_order_end(MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    GPRCClass::iterator
-    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
-      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
-    }
-    GPRCClass::iterator
-    GPRCClass::allocation_order_end(MachineFunction &MF) const {
-      if (hasFP(MF))
-        return end()-4;
-      else
-        return end()-3;
-    }
-  }];
-}
-
-def F8RC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
-  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
-  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
-def F4RC : RegisterClass<"PPC32", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
-  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
-  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
-
-
-def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 41ec8db8f73036b30d64b6da6eba2edaba27b207..d8d38450f6e4bf7b3ba48089b35e146f9905c523 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -84,3 +84,39 @@ def LR : SPR<2,   "lr">;
 // Count register
 def CTR : SPR<3, "ctr">;
 
+/// Register classes
+// Allocate volatiles first
+// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
+def GPRC : RegisterClass<"PPC32", i32, 32,
+     [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
+      R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
+      R16, R15, R14, R13, R31, R0, R1, LR]>
+{
+  let MethodProtos = [{
+    iterator allocation_order_begin(MachineFunction &MF) const;
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GPRCClass::iterator
+    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
+      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
+    }
+    GPRCClass::iterator
+    GPRCClass::allocation_order_end(MachineFunction &MF) const {
+      if (hasFP(MF))
+        return end()-4;
+      else
+        return end()-3;
+    }
+  }];
+}
+
+def F8RC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+def F4RC : RegisterClass<"PPC32", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
+  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
+
+def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;

diff --git a/lib/Target/PowerPC/PowerPC.td b/lib/Target/PowerPC/PowerPC.td
index e593fe4b9cebbf321f30cb842ebcc949f6c45a21..856ec25b558d80b20ba772030f1e0bddebffef32 100644 (file)
--- a/lib/Target/PowerPC/PowerPC.td
+++ b/lib/Target/PowerPC/PowerPC.td
@@ -18,7 +18,7 @@ include "../Target.td"
 // Register File Description
 //===----------------------------------------------------------------------===//
 
-include "PPC32RegisterInfo.td"
+include "PowerPCRegisterInfo.td"
 include "PowerPCInstrInfo.td"
 
 def PowerPC : Target {