Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 69f8a6459ef7223281a046fa3a6a00cff6d51f4a..64a3dc73ceef88709b911e5b045828e19782f9fa 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -851,6 +851,7 @@ multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
     bits<17> shift;
     let Inst{23}    = shift{12};    // U (add = ('U' == 1))
     let Inst{19-16} = shift{16-13}; // Rn
+    let Inst{15-12} = Rt;
     let Inst{11-0}  = shift{11-0};
   }
 }
@@ -879,6 +880,7 @@ multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
     bits<17> shift;
     let Inst{23}    = shift{12};    // U (add = ('U' == 1))
     let Inst{19-16} = shift{16-13}; // Rn
+    let Inst{15-12} = Rt;
     let Inst{11-0}  = shift{11-0};
   }
 }