unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
- if (SubIdx == Mips::sub_hi && FP64)
- BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg);
- else
+ if (SubIdx == Mips::sub_hi && FP64) {
+ // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to
+ // temporarily work around a widespread bug in the -mfp64 support.
+ // The problem is that none of the 32-bit fpu ops mention the fact
+ // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
+ // requires a major overhaul of the FPU implementation which can't
+ // be done right now due to time constraints.
+ // MFHC1 is the only instruction that is affected since it is the
+ // only instruction that doesn't read the lower 32-bits. We therefore
+ // pretend that it reads the bottom 32-bits to artificially create a
+ // dependency and prevent the scheduler changing the behaviour of the
+ // code.
+ BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
+ SrcReg, RegState::Implicit);
+ } else
BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
}