// Instructions introduced in AVX (no SSE equivalent forms)
//
// AVX8I - AVX instructions with T8 and OpSize prefix.
+// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
Requires<[HasAVX]>;
+class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag> pattern>
+ : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
+ Requires<[HasAVX]>;
// AES Instruction Templates:
//
def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem>;
def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem>;
+// Insert packed floating-point values
+def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
+ (ins VR256:$src1, VR128:$src2, i8imm:$src3),
+ "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, VEX_4V;
+def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
+ (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
+ "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, VEX_4V;
+
} // isAsmParserOnly
// CHECK: encoding: [0xc4,0xe2,0x7d,0x18,0x10]
vbroadcastss (%eax), %ymm2
+// CHECK: vinsertf128 $7, %xmm2, %ymm2, %ymm5
+// CHECK: encoding: [0xc4,0xe3,0x6d,0x18,0xea,0x07]
+ vinsertf128 $7, %xmm2, %ymm2, %ymm5
+
+// CHECK: vinsertf128 $7, (%eax), %ymm2, %ymm5
+// CHECK: encoding: [0xc4,0xe3,0x6d,0x18,0x28,0x07]
+ vinsertf128 $7, (%eax), %ymm2, %ymm5
+
// CHECK: encoding: [0xc4,0x62,0x7d,0x18,0x20]
vbroadcastss (%rax), %ymm12
+// CHECK: vinsertf128 $7, %xmm12, %ymm12, %ymm10
+// CHECK: encoding: [0xc4,0x43,0x1d,0x18,0xd4,0x07]
+ vinsertf128 $7, %xmm12, %ymm12, %ymm10
+
+// CHECK: vinsertf128 $7, (%rax), %ymm12, %ymm10
+// CHECK: encoding: [0xc4,0x63,0x1d,0x18,0x10,0x07]
+ vinsertf128 $7, (%rax), %ymm12, %ymm10
+