Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index be35187a8d532ca8c64afd6098632d9a462a62cc..02ad1695a645cbadc8bea03eff4206f8ce937999 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -2014,6 +2014,12 @@ let Predicates = [HasTBM] in {
   def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
             (BLCI_64rr GR64:$src)>;
 
+  // Extra patterns because opt can optimize the above patterns to this.
+  def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
+            (BLCI_32rr GR32:$src)>;
+  def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
+            (BLCI_64rr GR64:$src)>;
+
   def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
             (BLCIC_32rr GR32:$src)>;
   def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),

diff --git a/test/CodeGen/X86/tbm_patterns.ll b/test/CodeGen/X86/tbm_patterns.ll
index 8b999be0ea72eef69c427b51f15dfa80af4bed71..79eea10af3ae0919dc7979afad20c67d2191fd88 100644 (file)
--- a/test/CodeGen/X86/tbm_patterns.ll
+++ b/test/CodeGen/X86/tbm_patterns.ll
@@ -84,6 +84,26 @@ entry:
   ret i64 %2
 }
 
+define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind readnone {
+entry:
+  ; CHECK-LABEL: test_x86_tbm_blci_u32_b:
+  ; CHECK-NOT: mov
+  ; CHECK: blci %
+  %0 = sub i32 -2, %a
+  %1 = or i32 %0, %a
+  ret i32 %1
+}
+
+define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind readnone {
+entry:
+  ; CHECK-LABEL: test_x86_tbm_blci_u64_b:
+  ; CHECK-NOT: mov
+  ; CHECK: blci %
+  %0 = sub i64 -2, %a
+  %1 = or i64 %0, %a
+  ret i64 %1
+}
+
 define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
 entry:
   ; CHECK-LABEL: test_x86_tbm_blcic_u32: