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clk: rockchip: pll: use reg offset instead of reg
authordkl <dkl@rock-chips.com>
Wed, 18 Jun 2014 01:24:02 +0000 (09:24 +0800)
committerdkl <dkl@rock-chips.com>
Wed, 18 Jun 2014 01:27:53 +0000 (09:27 +0800)
drivers/clk/rockchip/clk-pll.c patch | blob | history
drivers/clk/rockchip/clk-pll.h patch | blob | history
drivers/clk/rockchip/clk.c patch | blob | history

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4045fad75d7eaf79b5b48f63a4642cc9c0909df8..2f54724a6a6b252e016ecfb8992adc2a3a4520d7 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -188,10 +188,10 @@ static void pll_wait_lock(struct clk_hw *hw)
                                "pll_con2=%08x\npll_con3=%08x\n",
                                __clk_get_name(hw->clk),
                                pll->status_shift,
-                               readl(pll->reg + RK3188_PLL_CON(0)),
-                               readl(pll->reg + RK3188_PLL_CON(1)),
-                               readl(pll->reg + RK3188_PLL_CON(2)),
-                               readl(pll->reg + RK3188_PLL_CON(3)));
+                               cru_readl(pll->reg + RK3188_PLL_CON(0)),
+                               cru_readl(pll->reg + RK3188_PLL_CON(1)),
+                               cru_readl(pll->reg + RK3188_PLL_CON(2)),
+                               cru_readl(pll->reg + RK3188_PLL_CON(3)));
 
                while(1);
        }
@@ -252,8 +252,8 @@ static unsigned long clk_pll_recalc_rate_3188(struct clk_hw *hw,
 
 
        if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
-               u32 pll_con0 = readl(pll->reg + RK3188_PLL_CON(0));
-               u32 pll_con1 = readl(pll->reg + RK3188_PLL_CON(1));
+               u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
+               u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
 
                u64 rate64 = (u64)parent_rate * RK3188_PLL_NF(pll_con1);
 
@@ -301,20 +301,20 @@ static int _pll_clk_set_rate_3188(struct pll_clk_set *clk_set,
        //enter slowmode
        cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
        //pll power down
-       writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+       cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
        dsb();
        dsb();
        dsb();
        dsb();
        dsb();
        dsb();
-       writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
-       writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
+       cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
+       cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
 
        udelay(1);
 
        //pll no power down
-       writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
+       cru_writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
 
        pll_wait_lock(hw);
 
@@ -326,8 +326,8 @@ static int _pll_clk_set_rate_3188(struct pll_clk_set *clk_set,
 
        clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
                        __clk_get_name(hw->clk),
-                       readl(pll->reg + RK3188_PLL_CON(0)),
-                       readl(pll->reg + RK3188_PLL_CON(1)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(0)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(1)),
                        cru_readl(pll->mode_offset));
 
        clk_debug("%s end!\n", __func__);
@@ -349,7 +349,7 @@ static int clk_pll_set_rate_3188(struct clk_hw *hw, unsigned long rate,
                cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
                                pll->mode_offset);
                /* pll power down */
-               writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+               cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
                clk_debug("pll %s enter slow mode, set rate OK!\n",
                                __clk_get_name(hw->clk));
                return 0;
@@ -426,7 +426,7 @@ static int clk_pll_set_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
                cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
                                pll->mode_offset);
                /* pll power down */
-               writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+               cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
                clk_debug("pll %s enter slow mode, set rate OK!\n",
                                __clk_get_name(hw->clk));
                return 0;
@@ -511,20 +511,20 @@ CHANGE_APLL:
        cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
 
        /* PLL power down */
-       writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+       cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
        dsb();
        dsb();
        dsb();
        dsb();
        dsb();
        dsb();
-       writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
-       writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
+       cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
+       cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
 
        udelay(1);
 
        /* PLL power up and wait for locked */
-       writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
+       cru_writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
        pll_wait_lock(hw);
 
        old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
@@ -569,10 +569,10 @@ CHANGE_APLL:
 
        clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
                        ps->rate,
-                       readl(pll->reg + RK3188_PLL_CON(0)),
-                       readl(pll->reg + RK3188_PLL_CON(1)),
-                       readl(pll->reg + RK3188_PLL_CON(2)),
-                       readl(pll->reg + RK3188_PLL_CON(3)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(0)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(1)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(2)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(3)),
                        cru_readl(RK3188_CRU_CLKSELS_CON(0)),
                        cru_readl(RK3188_CRU_CLKSELS_CON(1)));
 
@@ -595,8 +595,8 @@ static unsigned long clk_pll_recalc_rate_3188plus(struct clk_hw *hw,
 
 
        if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
-               u32 pll_con0 = readl(pll->reg + RK3188_PLL_CON(0));
-               u32 pll_con1 = readl(pll->reg + RK3188_PLL_CON(1));
+               u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
+               u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
 
                u64 rate64 = (u64)parent_rate * RK3188PLUS_PLL_NF(pll_con1);
 
@@ -645,16 +645,16 @@ static int _pll_clk_set_rate_3188plus(struct pll_clk_set *clk_set,
        cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
 
        //enter rest
-       writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
+       cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
 
-       writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
-       writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
-       writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
+       cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
+       cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
+       cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
 
        udelay(5);
 
        //return from rest
-       writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
+       cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
 
        //wating lock state
        udelay(clk_set->rst_dly);
@@ -669,8 +669,8 @@ static int _pll_clk_set_rate_3188plus(struct pll_clk_set *clk_set,
 
        clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
                        __clk_get_name(hw->clk),
-                       readl(pll->reg + RK3188_PLL_CON(0)),
-                       readl(pll->reg + RK3188_PLL_CON(1)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(0)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(1)),
                        cru_readl(pll->mode_offset));
 
        clk_debug("%s end!\n", __func__);
@@ -692,7 +692,7 @@ static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
                cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
                                pll->mode_offset);
                /* pll power down */
-               writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+               cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
                clk_debug("pll %s enter slow mode, set rate OK!\n",
                                __clk_get_name(hw->clk));
                return 0;
@@ -946,7 +946,7 @@ static int clk_pll_set_rate_3188plus_apll(struct clk_hw *hw, unsigned long rate,
                cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
                                pll->mode_offset);
                /* pll power down */
-               writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+               cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
                clk_debug("pll %s enter slow mode, set rate OK!\n",
                                __clk_get_name(hw->clk));
                return 0;
@@ -1032,16 +1032,16 @@ CHANGE_APLL:
        cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
 
        /* PLL enter rest */
-       writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
+       cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
 
-       writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
-       writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
-       writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
+       cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
+       cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
+       cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
 
        udelay(5);
 
        /* return from rest */
-       writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
+       cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
 
        //wating lock state
        udelay(ps->rst_dly);
@@ -1089,10 +1089,10 @@ CHANGE_APLL:
 
        clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
                        ps->rate,
-                       readl(pll->reg + RK3188_PLL_CON(0)),
-                       readl(pll->reg + RK3188_PLL_CON(1)),
-                       readl(pll->reg + RK3188_PLL_CON(2)),
-                       readl(pll->reg + RK3188_PLL_CON(3)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(0)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(1)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(2)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(3)),
                        cru_readl(RK3188_CRU_CLKSELS_CON(0)),
                        cru_readl(RK3188_CRU_CLKSELS_CON(1)));
 
@@ -1150,7 +1150,7 @@ static int clk_pll_set_rate_3288_apll(struct clk_hw *hw, unsigned long rate,
                cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
                                pll->mode_offset);
                /* pll power down */
-               writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
+               cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
                clk_debug("pll %s enter slow mode, set rate OK!\n",
                                __clk_get_name(hw->clk));
                return 0;
@@ -1251,16 +1251,16 @@ CHANGE_APLL:
        cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
 
        /* PLL enter rest */
-       writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
+       cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
 
-       writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
-       writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
-       writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
+       cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
+       cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
+       cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
 
        udelay(5);
 
        /* return from rest */
-       writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
+       cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
 
        //wating lock state
        udelay(ps->rst_dly);
@@ -1323,10 +1323,10 @@ CHANGE_APLL:
 
        clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
                        ps->rate,
-                       readl(pll->reg + RK3188_PLL_CON(0)),
-                       readl(pll->reg + RK3188_PLL_CON(1)),
-                       readl(pll->reg + RK3188_PLL_CON(2)),
-                       readl(pll->reg + RK3188_PLL_CON(3)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(0)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(1)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(2)),
+                       cru_readl(pll->reg + RK3188_PLL_CON(3)),
                        cru_readl(RK3288_CRU_CLKSELS_CON(0)),
                        cru_readl(RK3288_CRU_CLKSELS_CON(1)));
 
@@ -1370,7 +1370,7 @@ const struct clk_ops *rk_get_pll_ops(u32 pll_flags)
 }
 
 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
-               const char *parent_name, unsigned long flags, void __iomem *reg,
+               const char *parent_name, unsigned long flags, u32 reg,
                u32 width, u32 mode_offset, u8 mode_shift,
                u32 status_offset, u8 status_shift, u32 pll_flags,
                spinlock_t *lock)
diff --git a/drivers/clk/rockchip/clk-pll.h b/drivers/clk/rockchip/clk-pll.h
index b985be91d0e3604d8579d2c4c7e5597420e4b885..2479cb45ca2a31ff7d85b6eed16efb3e3f2edaff 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.h
+++ b/drivers/clk/rockchip/clk-pll.h
@@ -282,7 +282,7 @@ struct apll_clk_set {
 
 struct clk_pll {
        struct clk_hw   hw;
-       void __iomem    *reg;
+       u32             reg;
        u32             width;
        u32             mode_offset;
        u8              mode_shift;
@@ -296,7 +296,7 @@ struct clk_pll {
 const struct clk_ops *rk_get_pll_ops(u32 pll_flags);
 
 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
-               const char *parent_name, unsigned long flags, void __iomem *reg,
+               const char *parent_name, unsigned long flags, u32 reg,
                u32 width, u32 mode_offset, u8 mode_shift,
                u32 status_offset, u8 status_shift, u32 pll_flags,
                spinlock_t *lock);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 122f646dbbc82873a7c6ec1e28b31504f6eca552..aaad37e87a7e3b4412b413c59c4d81e99bab8802 100755 (executable)
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -667,7 +667,6 @@ static int __init rkclk_init_pllcon(struct device_node *np)
 {
        struct device_node *node = NULL;
        struct rkclk_pllinfo *pllinfo = NULL;
-       void __iomem    *reg;
        struct clk_pll *pll = NULL;
        u8 found = 0;
        int ret = 0;
@@ -704,14 +703,11 @@ static int __init rkclk_init_pllcon(struct device_node *np)
                        flags = 0;
                        ret = 0;
                }
-
-               reg = of_iomap(node, 0);
-               if (reg == NULL) {
+       
+               ret = of_property_read_u32_index(node, "reg", 0, &pll->reg);
+               if (ret != 0) {
                        clk_err("%s: can not get reg addr info\n", __func__);
-                       ret = -EINVAL;
                        goto out;
-               } else {
-                       pll->reg = reg;
                }
 
                ret = of_property_read_u32_index(node, "reg", 1, &pll->width);
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