CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
BRFCC, // Branch to dest on fcc condition
+
+ Hi, Lo, // Hi/Lo operations, typically on a global address.
};
}
addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
+ // Custom legalize GlobalAddress nodes into LO/HI parts.
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
}
}
+ case ISD::GlobalAddress: {
+ GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
+ SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
+ SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
+ }
}
}
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
- R1 = Addr.getOperand(0);
- R2 = Addr.getOperand(1);
+ R1 = Select(Addr.getOperand(0));
+ R2 = Select(Addr.getOperand(1));
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
if (Predicate_simm13(CN)) {
- Base = Addr.getOperand(0);
+ Base = Select(Addr.getOperand(0));
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
+def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
+def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
//===----------------------------------------------------------------------===//
// Instructions
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
+
+// Global addresses
+def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
+def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
BRFCC, // Branch to dest on fcc condition
+
+ Hi, Lo, // Hi/Lo operations, typically on a global address.
};
}
addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
+ // Custom legalize GlobalAddress nodes into LO/HI parts.
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
}
}
+ case ISD::GlobalAddress: {
+ GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
+ SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
+ SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
+ }
}
}
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
- R1 = Addr.getOperand(0);
- R2 = Addr.getOperand(1);
+ R1 = Select(Addr.getOperand(0));
+ R2 = Select(Addr.getOperand(1));
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
if (Predicate_simm13(CN)) {
- Base = Addr.getOperand(0);
+ Base = Select(Addr.getOperand(0));
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
+def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
+def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
//===----------------------------------------------------------------------===//
// Instructions
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
+
+// Global addresses
+def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
+def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;