reenable this hack, the tblgen version isn't quite ready

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 7ddf8c0104ddaf77dc987f204732edeaa617cba3..61e279c046ec754b675700b9374412292561c403 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -927,6 +927,22 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   
   switch (N->getOpcode()) {
   default: break;
+  case ISD::VECTOR_SHUFFLE:
+    // FIXME: This should be autogenerated from the .td file, it is here for now
+    // due to bugs in tblgen.
+    if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
+        (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
+        PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
+      SDOperand N0;
+      Select(N0, N->getOperand(0));
+      Result = CodeGenMap[Op] = 
+        SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
+                                        getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
+                                        N0), 0);
+      return;
+    }
+    assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
+      
   case ISD::SETCC:
     Result = SelectSETCC(Op);
     return;