CHROMIUM: usb: dwc3: add usb3_warm_reset_on_resume_quirk
authorWilliam wu <wulf@rock-chips.com>
Mon, 21 Nov 2016 07:32:26 +0000 (15:32 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Thu, 20 Apr 2017 08:29:02 +0000 (16:29 +0800)
This patch add a quirk for some special platforms (e.g. rk3399
platform) which need to do warm reset for USB3 device on resume.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I19acc0560001481e5a952175433e82d17dfb3a40
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412488
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Documentation/devicetree/bindings/usb/dwc3.txt
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
drivers/usb/dwc3/host.c

index 23633568cfcc6cc219d718fcd2bbc301d4646fe1..408639c20c8ca0f7ba23a16203d980207f443ce7 100644 (file)
@@ -59,6 +59,7 @@ Optional properties:
  - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
        register for post-silicon frame length adjustment when the
        fladj_30mhz_sdbnd signal is invalid or incorrect.
+ - snps,usb3-warm-reset-on-resume-quirk: when set, need warm reset on resume.
 
  - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
 
index acc6831eaf9570ce170ecc995c7adb08ff760ae5..3efc7d896ac99d6c87e8f74eae7bd0e2b2548ccb 100644 (file)
@@ -999,6 +999,8 @@ static int dwc3_probe(struct platform_device *pdev)
                                "snps,tx-ipgap-linecheck-dis-quirk");
        dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
                                "snps,xhci-slow-suspend-quirk");
+       dwc->usb3_warm_reset_on_resume_quirk = device_property_read_bool(dev,
+                               "snps,usb3-warm-reset-on-resume-quirk");
 
        dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
                                "snps,tx_de_emphasis_quirk");
index 1e56b9b62b9a2399a7ccb16f1912d4d82d030fe1..2a38687ae99d28ea6084cb742a771fb1f941ce65 100644 (file)
@@ -821,6 +821,7 @@ struct dwc3_scratchpad_array {
  * @xhci_slow_suspend_quirk: set if need an extraordinary delay to wait
  *                     for xHC enter the Halted state after the Run/Stop
  *                     (R/S) bit is cleared to '0'.
+ * @usb3_warm_reset_on_resume_quirk: set if need a warm reset on resume
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  *     0       - -6dB de-emphasis
@@ -971,6 +972,7 @@ struct dwc3 {
        unsigned                dis_del_phy_power_chg_quirk:1;
        unsigned                tx_ipgap_linecheck_dis_quirk:1;
        unsigned                xhci_slow_suspend_quirk:1;
+       unsigned                usb3_warm_reset_on_resume_quirk:1;
 
        unsigned                tx_de_emphasis_quirk:1;
        unsigned                tx_de_emphasis:2;
index 489ab425e177a431ada294c2e47d85f78ed83f3d..f92971cccd86a02984b28363c3a6e524cdf0413e 100644 (file)
@@ -94,6 +94,7 @@ int dwc3_host_init(struct dwc3 *dwc)
        pdata.usb3_disable_autosuspend = dwc->dis_u3_autosuspend_quirk;
        pdata.usb3_lpm_capable = dwc->usb3_lpm_capable;
        pdata.xhci_slow_suspend = dwc->xhci_slow_suspend_quirk;
+       pdata.usb3_warm_reset_on_resume = dwc->usb3_warm_reset_on_resume_quirk;
 
        ret = platform_device_add_data(xhci, &pdata, sizeof(pdata));
        if (ret) {