Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94455 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index d393e8d7e3e26e58a8cf93b5eb57fe7c01be976e..e4b18088ad66a1577d9c4be6562a0255b510ae95 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -123,7 +123,7 @@ def FPSCR : ARMReg<1, "fpscr">;
 // r10 == Stack Limit
 //
 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
-                                           R7, R8, R9, R10, R12, R11,
+                                           R7, R8, R9, R10, R11, R12,
                                            LR, SP, PC]> {
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;