Convert some more Neon tests to FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80120 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/vcls.ll b/test/CodeGen/ARM/vcls.ll
index 69e4bdbe163e5ad98187f0386ae6d944aed30382..25b94db729de903baaeedac16382c99a736a66aa 100644 (file)
--- a/test/CodeGen/ARM/vcls.ll
+++ b/test/CodeGen/ARM/vcls.ll
@@ -1,39 +1,48 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vcls\\.s8} %t | count 2
-; RUN: grep {vcls\\.s16} %t | count 2
-; RUN: grep {vcls\\.s32} %t | count 2
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
+;CHECK: vclss8:
+;CHECK: vcls.s8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
        ret <8 x i8> %tmp2
 }
 
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
+;CHECK: vclss16:
+;CHECK: vcls.s16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
        ret <4 x i16> %tmp2
 }
 
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
+;CHECK: vclss32:
+;CHECK: vcls.s32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
        ret <2 x i32> %tmp2
 }
 
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
+;CHECK: vclsQs8:
+;CHECK: vcls.s8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
        ret <16 x i8> %tmp2
 }
 
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
+;CHECK: vclsQs16:
+;CHECK: vcls.s16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
        ret <8 x i16> %tmp2
 }
 
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
+;CHECK: vclsQs32:
+;CHECK: vcls.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
        ret <4 x i32> %tmp2

diff --git a/test/CodeGen/ARM/vclz.ll b/test/CodeGen/ARM/vclz.ll
index 575ea7d2e848d6bcad47bc947b8e51060989c1e5..cd9daa5d8b4795ba548e14484fbf582a51a49cb2 100644 (file)
--- a/test/CodeGen/ARM/vclz.ll
+++ b/test/CodeGen/ARM/vclz.ll
@@ -1,39 +1,48 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vclz\\.i8} %t | count 2
-; RUN: grep {vclz\\.i16} %t | count 2
-; RUN: grep {vclz\\.i32} %t | count 2
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
+;CHECK: vclz8:
+;CHECK: vclz.i8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1)
        ret <8 x i8> %tmp2
 }
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
+;CHECK: vclz16:
+;CHECK: vclz.i16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
        ret <4 x i16> %tmp2
 }
 
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
+;CHECK: vclz32:
+;CHECK: vclz.i32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1)
        ret <2 x i32> %tmp2
 }
 
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
+;CHECK: vclzQ8:
+;CHECK: vclz.i8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1)
        ret <16 x i8> %tmp2
 }
 
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
+;CHECK: vclzQ16:
+;CHECK: vclz.i16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
        ret <8 x i16> %tmp2
 }
 
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
+;CHECK: vclzQ32:
+;CHECK: vclz.i32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32> %tmp1)
        ret <4 x i32> %tmp2

diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll
index 981716895894e46cd73445b44494b681374ae736..bf98eefa92bbbafc53c278b87132079f67c98f6f 100644 (file)
--- a/test/CodeGen/ARM/vcnt.ll
+++ b/test/CodeGen/ARM/vcnt.ll
@@ -1,13 +1,16 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vcnt\\.8} %t | count 2
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+;CHECK: vcnt8:
+;CHECK: vcnt.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
        ret <8 x i8> %tmp2
 }
 
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
+;CHECK: vcntQ8:
+;CHECK: vcnt.8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1)
        ret <16 x i8> %tmp2

diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll
index 1cb42bf155cb775b2c414f4166d8f2ad48f0cb95..b89b82b12966b6d8dc96f0183032cffbffb33ada 100644 (file)
--- a/test/CodeGen/ARM/vcvt.ll
+++ b/test/CodeGen/ARM/vcvt.ll
@@ -1,52 +1,64 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vcvt\\.s32\\.f32} %t | count 2
-; RUN: grep {vcvt\\.u32\\.f32} %t | count 2
-; RUN: grep {vcvt\\.f32\\.s32} %t | count 2
-; RUN: grep {vcvt\\.f32\\.u32} %t | count 2
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
 
 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_f32tos32:
+;CHECK: vcvt.s32.f32
        %tmp1 = load <2 x float>* %A
        %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
        ret <2 x i32> %tmp2
 }
 
 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_f32tou32:
+;CHECK: vcvt.u32.f32
        %tmp1 = load <2 x float>* %A
        %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
        ret <2 x i32> %tmp2
 }
 
 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_s32tof32:
+;CHECK: vcvt.f32.s32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
        ret <2 x float> %tmp2
 }
 
 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_u32tof32:
+;CHECK: vcvt.f32.u32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
        ret <2 x float> %tmp2
 }
 
 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_f32tos32:
+;CHECK: vcvt.s32.f32
        %tmp1 = load <4 x float>* %A
        %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
        ret <4 x i32> %tmp2
 }
 
 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_f32tou32:
+;CHECK: vcvt.u32.f32
        %tmp1 = load <4 x float>* %A
        %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
        ret <4 x i32> %tmp2
 }
 
 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_s32tof32:
+;CHECK: vcvt.f32.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
        ret <4 x float> %tmp2
 }
 
 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_u32tof32:
+;CHECK: vcvt.f32.u32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
        ret <4 x float> %tmp2