drm/rockchip: dsi: Documentation: modify the dsi node

1. rename mipi_dsi to dsi0
2. add some properties, such as dual-channel
3. add dsi1 node

Change-Id: I623d31e26ce21f28036a0f665f3e69d8d60b199b
Signed-off-by: Jerry Xu <xbl@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index f6ebe3ec40e57e37acc014f5749135674b6ce440..dd6e29c28d6213ac964fe970a3f1187ef9b030c5 100644 (file)
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -2,8 +2,6 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI
 ================================
 
 Required properties:
-- #address-cells: Should be <1>.
-- #size-cells: Should be <0>.
 - compatible: must be one of:
        "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
        "rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
@@ -14,6 +12,8 @@ Required properties:
 - clocks, clock-names: Phandles to the controller's APB clock(pclk) as
   described in [1].
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
 
@@ -27,6 +27,8 @@ Optional properties
   attribute, provides phandle to MIPI PHY node
 - resets : phandle to the reset of MIPI DSI APB Clock.
 - reset-names : should be "apb".
+- rockchip,dual-channel: for dual-channel panel, if not, don't configure
+- rockchip,lane-rate: manually configure lane-rate, not necessary.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
@@ -36,16 +38,19 @@ Example:
 
 For Rockchip RK3288:
 
-       mipi_dsi: mipi@ff960000 {
-               #address-cells = <1>;
-               #size-cells = <0>;
+       dsi0: dsi@ff960000 {
                compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
-               reg = <0xff960000 0x4000>;
-               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>,
-                        <&cru SCLK_DPHY_TX0_CFG>;
-               clock-names = "ref", "pclk", "phy_cfg";
+               reg = <0x0 0xff960000 0x0 0x4000>;
+               interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+               clock-names = "ref", "pclk";
                rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               rockchip,dual-channel = <&dsi1>;
+               rockchip,lane-rate = <900>;
+
                status = "okay";
 
                ports {
@@ -53,16 +58,17 @@ For Rockchip RK3288:
                        #size-cells = <0>;
                        reg = <1>;
 
-                       mipi_in: port {
+                       dsi0_in: port {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               mipi_in_vopb: endpoint@0 {
+
+                               dsi0_in_vopb: endpoint@0 {
                                        reg = <0>;
-                                       remote-endpoint = <&vopb_out_mipi>;
+                                       remote-endpoint = <&vopb_out_dsi0>;
                                };
-                               mipi_in_vopl: endpoint@1 {
+                               dsi0_in_vopl: endpoint@1 {
                                        reg = <1>;
-                                       remote-endpoint = <&vopl_out_mipi>;
+                                       remote-endpoint = <&vopl_out_dsi0>;
                                };
                        };
                };
@@ -79,6 +85,38 @@ For Rockchip RK3288:
                };
        };
 
+       dsi1: dsi@ff964000 {
+               compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+               reg = <0x0 0xff964000 0x0 0x4000>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI1>;
+               clock-names = "ref", "pclk";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "okay";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+
+                       dsi1_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               dsi1_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_dsi1>;
+                               };
+                               dsi1_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_dsi1>;
+                               };
+                       };
+               };
+       };
+
 For Rockchip RK3368:
 
        dsi: dsi@ff960000 {