{0x23bd, 0x0100}, {0x23be, 0x2400}, {0x23cf, 0x0800}, {0x23d0, 0x0400},
{0x23d1, 0xff80}, {0x23d2, 0xff80}, {0x23d3, 0x0800}, {0x23d4, 0x3e00},
{0x23d5, 0x5000}, {0x23e7, 0x0800}, {0x23e8, 0x0e00}, {0x23e9, 0x7000},
- {0x23ea, 0x7ff0}, {0x23ed, 0x0300}, {0x22fb, 0x0000},
+ {0x23ea, 0x7ff0}, {0x23ed, 0x0300}, {0x22fb, 0x0000}, {0x2328, 0x7fff},
};
#define RT3261_DSP_AEC_NUM \
(sizeof(rt3261_dsp_aec_ns_fens) / sizeof(rt3261_dsp_aec_ns_fens[0]))
return 0;
}
- ret = codec->hw_write(codec->control_data, data, len);
+ ret = i2c_master_normal_send(codec->control_data, data, len,400*1000);
if (ret == len)
return 0;
if (ret < 0)
data[1] = (value >> 8) & 0xff;
data[2] = value & 0xff;
+ DBG("rt3261_write 0x%x = 0x%x\n",reg,value);
return do_hw_write(codec, reg, value, data, 3);
}
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
return ret;
}
+ codec->write = rt3261_write;
#ifdef RT3261_PROC
rt3261_proc_init();
.remove = rt3261_remove,
.suspend = rt3261_suspend,
.resume = rt3261_resume,
+ .write = rt3261_write,
.set_bias_level = rt3261_set_bias_level,
.reg_cache_size = RT3261_VENDOR_ID2 + 1,
.reg_word_size = sizeof(u16),