Blackfin: work around anomaly 05000287
authorGraf Yang <graf.yang@analog.com>
Fri, 8 May 2009 07:42:12 +0000 (07:42 +0000)
committerMike Frysinger <vapier@gentoo.org>
Fri, 12 Jun 2009 10:11:31 +0000 (06:11 -0400)
Make sure we work around anomaly 05000287 by configuring different port
preferences for the data cache.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
arch/blackfin/kernel/cplb-mpu/cacheinit.c

index c6ff947f9d377ff30ec60a343deec485bc4390ae..d5a86c3017f7cfa8ca571f507224ac058881dbc7 100644 (file)
@@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
        }
 
        ctrl = bfin_read_DMEM_CONTROL();
-       ctrl |= DMEM_CNTR;
+
+       /*
+        *  Anomaly notes:
+        *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL
+        *  register, so that the port preferences for DAG0 and DAG1 are set
+        *  to port B
+        */
+       ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
        bfin_write_DMEM_CONTROL(ctrl);
        SSYNC();
 }