Don't charge the full latency for anti and output dependencies. This is

an area where eventually it would be good to use target-dependent
information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60498 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 73caea96b2e31e8d656ec2ef797b0029a013d68f..f3aef575f0757fd446c9e4315b89209a9e5baaee 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -160,9 +160,12 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
     for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
          P != PE; ++P) {
       SUnit *PredSU = P->Dep;
-      unsigned PredLatency = PredSU->CycleBound + PredSU->Latency;
-      if (SU->CycleBound < PredLatency) {
-        SU->CycleBound = PredLatency;
+      // This assumes that there's no delay for reusing registers.
+      unsigned PredLatency = (P->isCtrl && P->Reg != 0) ? 1 : PredSU->Latency;
+      unsigned PredTotalLatency = PredSU->CycleBound + PredLatency;
+      if (SU->CycleBound < PredTotalLatency ||
+          (SU->CycleBound == PredTotalLatency && !P->isAntiDep)) {
+        SU->CycleBound = PredTotalLatency;
         CriticalPath[*I] = &*P;
       }
     }