Add memory operand folding support for SHLD and SHRD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11905 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 77b9b0a720f76eb3365b9a1e33034b4f0ed3c50f..39d5c5261f91f4a577294d36392afa14e9dc657d 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -495,10 +495,14 @@ def SARmi16  : I2A8 <"sar", 0xC1, MRMS7m    >, OpSize;         // [mem16] >>>= i
 def SARmi32  : I2A8 <"sar", 0xC1, MRMS7m    >;                 // [mem32] >>>= imm32
 
 def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL;   // R32 <<= R32,R32 cl
+def SHLDmrCL32 : I2A8 <"shld", 0xA5, MRMDestMem>, TB, UsesCL;   // [mem32] <<= [mem32],R32 cl
 def SHLDrri32  : I2A8 <"shld", 0xA4, MRMDestReg>, TB;           // R32 <<= R32,R32 imm8
+def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8
 
 def SHRDrrCL32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL;   // R32 >>= R32,R32 cl
+def SHRDmrCL32 : I2A8 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL;   // [mem32] >>= [mem32],R32 cl
 def SHRDrri32  : I2A8 <"shrd", 0xAC, MRMDestReg>, TB;           // R32 >>= R32,R32 imm8
+def SHRDmri32  : I2A8 <"shrd", 0xAC, MRMDestMem>, TB;           // [mem32] >>= [mem32],R32 imm8
 
 // Condition code ops, incl. set if equal/not equal/...
 def SAHF     : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>;  // flags = AH

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index cb26abf8ac8ce4747a93362c2b024aa49967ca13..748cfc0260fdc63a7b4a9eadf9aee7c2cd1c3fff 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -98,6 +98,13 @@ static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
                  .addReg(MI->getOperand(1).getReg());
 }
 
+static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
+                                 MachineInstr *MI) {
+  return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
+      .addReg(MI->getOperand(1).getReg())
+      .addZImm(MI->getOperand(2).getImmedValue());
+}
+
 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
                                 MachineInstr *MI) {
   if (MI->getOperand(1).isImmediate())
@@ -215,6 +222,10 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
     case X86::SARri8:  NI = MakeMIInst(X86::SARmi8 , FrameIndex, MI); break;
     case X86::SARri16: NI = MakeMIInst(X86::SARmi16, FrameIndex, MI); break;
     case X86::SARri32: NI = MakeMIInst(X86::SARmi32, FrameIndex, MI); break;
+    case X86::SHLDrrCL32:NI = MakeMRInst( X86::SHLDmrCL32,FrameIndex, MI);break;
+    case X86::SHLDrri32: NI = MakeMRIInst(X86::SHLDmri32, FrameIndex, MI);break;
+    case X86::SHRDrrCL32:NI = MakeMRInst( X86::SHRDmrCL32,FrameIndex, MI);break;
+    case X86::SHRDrri32: NI = MakeMRIInst(X86::SHRDmri32, FrameIndex, MI);break;
     case X86::TESTrr8: NI = MakeMRInst(X86::TESTmr8 ,FrameIndex, MI); break;
     case X86::TESTrr16:NI = MakeMRInst(X86::TESTmr16,FrameIndex, MI); break;
     case X86::TESTrr32:NI = MakeMRInst(X86::TESTmr32,FrameIndex, MI); break;